LD7575

17

Leadtrend Technology Corporation

www.leadtrend.com.tw

LD7575-DS-04b November 2009

Revision History

Rev.

Date

Change Notice

00

07/21/’05

Original Specification.

01

07/28/’05

1.

Page 2, Remove the unexpected code “skype.lnk” before the “ordering information”.

2.

Page 4, Recommended operating condition, change the “min. supply voltage Vcc”

from 10V to 11V since the UVLO range is from 9V to 11V.

3.

Page 9, Add the gate resistor on figure 15 and figure 16 to avoid misunderstanding.

4.

Page 11, Add the description “Figure 17 shows its operation.” In the section of “OVP

on Vcc”.

5.

Page 13, Add “Vin=264Vac” on the title.

02

10/24/’05

1.

Add DIP-8 Package

a.

Page 1 --- modify the general description “The LD7575 is offered in both

SOP-8 and DIP-8 package.”.

b.

Page 2 --- Add DIP-8 data on the “pin configuration” and “ordering

information”.

c.

Page 4 --- Add DIP-8 data on the “absolute maximum rating”.

d.

Page 15 --- Add DIP-8 package drawing

2.

Add information of HV current limit resistor and gate-to-GND resistor

a.

Page 1, 8 (figure13), 9 (figure15,16), 12, 13 --- Update the drawing, BOM and

schematics for such resistors.

b.

Page 11, 12 --- Add the sections “Pull-Low Resistor on the Gate Pin of

MOSFET”, “Protection Resistor on the Hi-V Path” and figure 19~22.

c.

Page 4 --- Add negative voltage limitation of HV pin on the “absolute maximum

rating”.

3.

Correction on the block diagram

a.

Page 3 --- Add flip-flop on the OVP loop to be matched with the OVP operation

and add the anti-floating resistor on the output.

4.

Correction on the description of Over Load Protection (OLP)

a.

Page 10 --- Original description “Whenever….30mS (when switching

frequency is 100KHz)”. Where the “100KHz” should be corrected to “65KHz”.

03

11/28/’05

1.

Page3, Correction on the block diagram by modifying the AND gate (following the

PWM comparator) to OR gate.

2.

Page 5, Correction on the parameters on “Gate Drive Output” because LD7575 can

support to 500mA driving capability but the parameters in the previous datasheet are

for 300mA driving current. The output high level will be updated from min. 8V to min.

9V. The rising time will be updated from max. 200nS to max. 160nS. The falling time

will be updated from max. 100nS to max. 60nS. All these parameters are for

correction and no design change on the related circuits.

04

1/22/’07

Revision: Block Diagram

04a

6/16/08

1.

Application information/ Protection Resistor on the Hi-V Path/ ……a 40K

Ω resistor is

recommended to implement on…..

2.

Additional option for Green package

04b

6/30

Protection resistor on the Hi-V Path: …..a 40K

Ω resistor is recommended….

Continued…