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LD5525GL Datasheet(PDF) 12 Page - Leadtrend Technology |
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LD5525GL Datasheet(HTML) 12 Page - Leadtrend Technology |
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12 / 16 page ![]() LD5525 06/30/2015 12 Leadtrend Technology Corporation www.leadtrend.com.tw LD5525-DS-00 June 2015 Adjustable Over Current Compensation on FB Pin For compensating the differential input current from high/low line conditions on current sensing resistor, LD5525 mirrors a compensation current IOCP from IFB to CS pin. The relationship of compensation current IOCP and IFB is expressed by following equation and shown in Fig. 13. FB OCP I K I × = , where 5 . 0 = K K is the mirror current ratio of FB pin, and the IOCP follows to the input voltage. The compensation current IOCP supplies an offset voltage by external resistor ROCP, which is series between the current sensing resistor RS and CS pin. By selecting a proper value of the resistor ROCP in series with the CS pin, the amount of compensation can be adjusted. IFB IOCP 95uA 400uA 47.5uA 200uA Fig. 13 Brown-In/ Brown-Out Protection (BNI/BNO) – Auto Recovery The LD5525 integrate the brown in, brownout protection and valley detection into FB pin. The auxiliary voltage reflects a proportional bulk voltage during the on time. Fix the internal current at the BNI and BNO, the BNI level could be set by modulating the FB divided resistors and auxiliary voltage, as shown in Fig. 14. For preventing the abnormal condition of line voltage to causing damage, BNO function is implemented, while turns off the gate signal after de-bounce time 60ms as BNO occurring, as shown in Fig. 15. The relationship of input voltage and BNI/BNO is expressed in following equation. ������������_������������ = �������� �������� ∙ ���������������� ∙ ����1 ������������_������������ = �������� �������� ∙ ���������������� ∙ ����1 ,where VDC_BNI is predicted BNI DC value of input voltage VDC_BNO is predicted BNO DC value of input voltage IBNI is BNI trip current. IBNO is BNO trip current. Np is turns ration of primary-side winding Na is turns ration of auxiliary winding LD5525 R1 R2 VCC FB GND Va VFB Fig. 14 |
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