 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
FS9912 Datasheet(PDF) 26 Page - Fortune Semiconductor Corp. |
|
|
|||||||||||||||||||||||||||||
FS9912 Datasheet(HTML) 26 Page - Fortune Semiconductor Corp. |
|
|
26 / 34 page  FS9912 Rev. 3.6 26/34 e. Set LOAD=0, FCRST=1, and P1.2 frequency starts measuring. f. Wait till positive edge of P1.2, then Start=1 and CTA and CTB start counting. g. Wait till CTA overflows and at the next positive edge of P1.2, then Start=0 and CTA and CTB stop counting. h. When the CPU receives interrupt signal, the CPU will read CTA and CTB. Here CTA is the reference clock counter, and CTB counts when P1.2=1. i. The duty cycle of P1.2 is 100% x CTB/(CTA+CTAI). Go to “a” for next measurement. C. Timer Mode: FCM=10 a. Load=1, FCRST=0 b. Write 14h and 15h to CTA [23:8] to set initial value of CTAI. c. Set GT [2:0] to select the length of counter CTA. GT=000 sets CTA [23:8] as a 16-bit counter and CTA [7] is as the clock input; CTA [23:0] is a 24-bit counter. GT=111 sets CTA [23:8] as a 16-bit counter and CTA [0] is as the clock input; {CTA [23:8], CTA [0]} is set as a 17-bit counter. d. Gate Time = (1000000h-CTAI x 256) x 1us … if GT=000 e. When CTA overflows, then send interrupt signal to the CPU. f. If CPU receives interrupt signal, then Go to “a”. 11.6 Measurement Part Block Diagram Analog to Digital Converter SOP1P=111 SOP1P=110 SOP1P=101 SOP1P=100 SOP1P=011 SOP1P=010 SOP1P=001 SOP1P=000 OP1 + - SINH=111 SINH=110 SINH=101 SINH=100 SINH=011 SINH=010 SINH=001 SINH=000 SFTA=1 SFT=00 SFT=01 SFT=10 SFT=11 SVRH=1 SVRH=0 SVRL=1 SVRL=0 AGND AD1 AGND AD6 AD5 AD0 AD3 AD4 AD2 AD0 AD4 AD5 VDD OP1P VRL VRH OP1O SINL=11 SINL=10 SINL=01 SINL=00 AD4 AD0 REFI ADINH ADINL VRH VRL AD1 AD4 AGND AD7 ADO[15:0] ADCGB[1:0] AZ ADEN ADRST AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD0 REFI AGND SONE=1 SONE=0 FTIN ENOP OP1P 11.7 ADC Address Name Content 010H ADOH ADO [15:8] 011H ADOL ADO [7:0] 013H ADCON ADRST 02BH NETC ADG1 ADG0 ADEN AZ The ADC (analog to digital converter) contains Σ-Δ modulator and digital comb filter. When ADRST=1, comb filter will be enabled. When ADRST=0, the comb filter will be reset. ADEN=1 starts the S-D |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
