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TP1561 Datasheet(PDF) 9 Page - 3PEAK INC. |
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TP1561 Datasheet(HTML) 9 Page - 3PEAK INC. |
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9 / 16 page ![]() 9 TP1561/TP1561N/TP1562/TP1564 Stable 3.8MHz, 130μA, RRIO, EveryCapTM Op Amps www.3peakic.com REV1.2 Figure 2 Shut-down The single channel OPA versions have SHDN pins that can shut down the amplifier to less than 0.2 μA supply current. The SHDN pin voltage needs to be within 0.5 V of V– for the amplifier to shut down. During shutdown, the output will be in high output resistance state, which is suitable for multiplexer applications. When left floating, the SHDN pin is internally pulled up to the positive supply and the amplifier remains enabled. Driving Large Capacitive Load The TP156x family of OPA is designed to drive large capacitive loads. Refer to Typical Performance Characteristics for “Phase Margin vs. Load Capacitance”. As always, larger load capacitance decreases overall phase margin in a feedback system where internal frequency compensation is utilized. As the load capacitance increases, the feedback loop’s phase margin decreases, and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in output step response. The unity-gain buffer (G = +1V/V) is the most sensitive to large capacitive loads. When driving large capacitive loads with the TP156x OPA family (e.g., > 200 pF when G = +1V/V), a small series resistor at the output (RISO in Figure 3) improves the feedback loop’s phase margin and stability by making the output load resistive at higher frequencies. Figure 3 Power Supply Layout and Bypass The TP156x OPA’s power supply pin (VDD for single-supply) should have a local bypass capacitor (i.e., 0.01 μF to 0.1 μF) within 2 mm for good high frequency performance. It can also use a bulk capacitor (i.e., 1μF or larger) within 100mm to provide large, slow currents. This bulk capacitor can be shared with other analog parts. Ground layout improves performance by decreasing the amount of stray capacitance and noise at the OPA’s inputs and outputs. To decrease stray capacitance, minimize PC board lengths and resistor leads, and place external components as close to the op amps’ pins as possible. Proper Board Layout To ensure optimum performance at the PCB level, care must be taken in the design of the board layout. To avoid leakage currents, the surface of the board should be kept clean and free of moisture. Coating the surface creates a barrier to moisture accumulation and helps reduce parasitic resistance on the board. |
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