HTG2190 datasheet(21/64 Pages) HOLTEK

21 / 64 page

HTG2190

Rev. 1.00

June 29, 2001

tion(s) in the program memory. Only the pro-

gram counter are pushed and A15~A13 bits

onto the stack. If the contents of the register

and Status register (STATUS) are altered by

the interrupt service program which corrupt

the desired control sequence, the contents must

be saved first.

External interrupt is triggered by a high to low

transition of INT which sets the related inter-

rupt request flag (EIF; bit 4 of INTC0). When

the interrupt is enabled, and the stack is not

full and the external interrupt is active, a sub-

routine call to location 04H will occur. The in-

terrupt request flag (EIF) and EMI bits will be

cleared to disable other interrupts.

The internal Timer/Event Counter 0 interrupt

is initialized by setting the Timer/Event Coun-

ter 0 interrupt request flag (T0F; bit 5 of

INTC0), caused by a Timer/Event Counter 0

overflow. When the interrupt is enabled, and

the stack is not full and the T0F bit is set, a sub-

routine call to location 08H will occur. The re-

lated interrupt request flag (T0F) will be reset

and the bit cleared to disable further inter-

rupts.

The Timer/Event Counter 1 and timer 2/3 inter-

rupt is operated in the same manner as

Timer/Event Counter 0. The related interrupt

control bits ET1I and T1F of Timer/Event

Counter 1 are bit 3 and bit 6 of INTC0 respec-

tively. While ET2I/ET3I and T2F/T3F are the

related control bits and the related request

flags of TMR2/TMR3, which locate at bit0/bit1

and bit4/bit5 of the INTC1 respectively.

During the execution of an interrupt subroutine,

other interrupt acknowledgments are held until

the RETI instruction is executed or the EMI bit

and the related interrupt control bit are set to 1 (of

course, if the stack is not full). To return from the

interrupt subroutine, the RET or RETI instruction

may be invoked. RETI will set the EMI bit to en-

able an interrupt service, but RET will not.

Interrupts occurring in the interval between

the rising edges of two consecutive T2 pulses,

will be serviced on the latter of the two T2

pulses, if the corresponding interrupts are en-

abled. In the case of simultaneous requests, the

following table shows the priority that is

applied. These can be masked by resetting the

EMI bit.

Bit No.

Label

Function

INTC0

EMI

Master (Global) interrupt

(1=enable; 0=disable)

EEI

External interrupt

(1=enable; 0=disable)

ET0I

Timer/Event Counter 0 interrupt

(1=enable; 0=disable)

ET1I

Timer/Event Counter 1 interrupt

(1=enable; 0=disable)

EIF

External interrupt request flag

(1=active; 0=inactive)

T0F

Internal Timer/Event Counter 0 request flag.

(1=active; 0=inactive)

T1F

Internal Timer/Event Counter 1 request flag.

(1=active; 0=inactive)

Unused bit, read as "0"

INTC0 register

HTG2190 Datasheet(PDF) 21 Page - Holtek Semiconductor Inc

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