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PV501BA Datasheet(PDF) 1 Page - NIKO SEMICONDUCTOR CO., LTD. |
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PV501BA Datasheet(HTML) 1 Page - NIKO SEMICONDUCTOR CO., LTD. |
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1 / 4 page ![]() P-Channel Logic Level Enhancement Mode Field Effect Transistor REV 1.0 1 F-53-3 PV501BA SOP-8 Halogen-free & Lead-Free NIKO-SEM G S D 100% UIS Tested 100% Rg Tested Features • Pb−Free, Halogen Free and RoHS compliant. • Low RDS(on) to Minimize Conduction Losses. • Ohmic Region Good RDS(on) Ratio. • Optimized Gate Charge to Minimize Switching Losses. • ESD Protected up to 2KV. Applications • Protection Circuits Applications. • Logic/Load Switch Circuits Applications. ABSOLUTE MAXIMUM RATINGS (TA = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS SYMBOL LIMITS UNITS Drain-Source Voltage VDS -30 V Gate-Source Voltage VGS ±25 V Continuous Drain Current TA = 25 °C ID -12 A TA = 70 °C -9.3 Pulsed Drain Current 1 IDM -50 Avalanche Current IAS -38 Avalanche Energy L = 0.1mH EAS 72 mJ Power Dissipation TA = 25 °C PD 1.8 W TA = 70 °C 1.1 Junction & Storage Temperature Range Tj, Tstg -55 to 150 °C THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM UNITS Junction-to-Ambient 2 RθJA 68 °C / W 1Pulse width limited by maximum junction temperature. 2 The value of R θJA is measured with the device mounted on 1in 2 FR-4 board with 2oz. Copper, in a still air environment with TA =25°C. G : GATE D : DRAIN S : SOURCE PRODUCT SUMMARY V(BR)DSS RDS(ON) ID -30V 7.5mΩ -12A |
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