EM5103VT datasheet(8/10 Pages) EXCELLIANCE

8 / 10 page

2011/11/14

Rev.A.8

EM5103

Functional Description

Enable Function

EM5103 is enabled if the voltage of the EN pin is

greater than 1.4V. If the voltage of the EN pin is

less than 0.4V, the IC will be disabled. The

quiescent current can be decreased to be less than

10uA typically.

POR – Power ON Reset

To let EM5103 start to operation, CNTL voltage

must be higher than its POR voltage even when EN

voltage is pulled higher than enable high voltage.

Typical POR voltage is 2.7V.

VOUT Voltage Adjustment

The VOUT voltage of EM5103 can be adjusted by

external

voltage

divider.

Refer

typical

application circuit, VOUT voltage is calculated by

the following equation,

VOUT = (1 + R1/R2) x 0.8V

Over Current Limit Function

EM5103 features over current limiting function as

well as output short circuit current fold back

function. Typically, before the thermal protection is

triggered, EM5103 can limit its output current to

4.0A. When output voltage is decreased, the

limiting current level also decreases. When VOUT is

short to GND, or VOUT voltage is zero, the output

current level is limited to 2.5A, typically.

Input and Output Capacitor Selection

For CNTL pin, a 1uF ceramic capacitor is enough for

bypass the supply of CNTL to GND. For VIN pin,

10uF or larger ceramic capacitor is required to

provide bypass path in transient current demand.

VOUT pin is also recommended to have 22uF or

larger ceramic capacitor to be stable and reduce

the VOUT voltage dip when fast loading transient is

happened. A feed-forward capacitor can be placed

between VOUT and FB pin to speed up the

transient response, optionally.

Power Dissipation

The max power depends on some conditions,

including of thermal impedance, PCB layout,

airflow, and so on. The max power dissipation can

be calculated by the formula as below

PD(max)=(TJ(max)-TA) / θJA

TJ(max) is the max junction temperature; θJA is the

thermal impedance from junction to ambient. The

thermal impedance θJA of exposed SOP-8 is

package design and PCB design dependent. The

thermal impedance can be reduced by increasing

the copper area under the exposed pad of the

SOP-8 package. So, to let the copper area as large

as possible is helpful for the thermal performance

of the exposed SOP-8 package.

For recommended specification of EM5103, the

max junction temperature is 125 degree C. The θJA

of exposed SOP-8 is 75°C/W on the standard JEDEC

51-7(4 layers, 2S2P, copper 2 oz) thermal test

board. The max power dissipation (at 25°C ambient,

on the min exposed pad layout) can be calculated

as below:

PD(max at 25°C)=(125°C–25°C)/(75°C/W) = 1.33W

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