ATR4255 datasheet(5/32 Pages) ATMEL

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ATR4255

4837A–AUDR–10/04

Test Mode

A special test mode is implemented for final production test only. This mode is activated

by setting bit 9 = 1. This mode is not intended to be used in customer application.

For normal operation, bit 9 has to be set to 0. Bit 18 to bit 30 are deactivated in normal

operation mode.

VCO

An oscillator circuit is implemented to build a VCO as proposed in the application sche-

matic. The VCO frequency is used to generate the LO frequency of the 1st mixer stages.

The control voltage of the VCO is usually generated by the PLL circuit U4256BM. The

VCO signal is provided at the buffered output pin 16 to be fed to the PLL circuit.

FM RF-AGC

The FM RF-AGC circuit includes a wideband level detector at the input pin 1 of the FM

mixer and an in-band level detector at the output of the FM IF amplifier (pin 30). The

outputs of these level detectors are used to control the current into the pin diode (see

Figure 3) in order to limit the signal level at the FM mixer input and the following stages.

The maximum pin diode current is determined by R115 and the time constant of the

AGC control loop can be adjusted by changing the value of C111.

The AGC threshold level at the input of the FM mixer can be adjusted by bit 64 and

bit 65 according to Table 3. The in-band AGC threshold referred to the FM mixer input

(pin 1, pin 2) depends on the gain of the FM IF amplifier and can be adjusted by bit 89

to bit 91.

Figure 3. FM RF-AGC Bit 92

Table 2. Test Mode

Mode

Bit 9

Normal operation

Testmode

Table 3. FM-AGC Threshold

FM-AGC Threshold

Bit 65

Bit 64

104 dBµV

101 dBµV

98 dBµV

92 dBµV

AGC

B92

PIN Diode

Pin 42

Pin 5

C111

R115

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