–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– s MSM7712 s

7

Oki Semiconductor

Shared RAM Interface

Local memory is provided for packet buffer and processor code and data. Memory size is flexible from

32K words to 128K words to support a range of applications (e.g. low-cost stations to high performance

access points).

Memory is word-sized to allow maximum performance in packet transfer rate. The design allows the use

of word-wide RAMs or a pair of byte-wide RAMs. The MSM7712 and host computer access shared RAM

in words only. The processor can access the RAM as odd or even bytes in addition to words.

For minimal cost applications local processor code may reside in shared memory. This may affect the

processor speed because accesses to shared memory may have wait states inserted.

The RAM access time is (1.5 clock cycles less 18 ns). Hence, with a MSM7712 clock (RCLK) of 16MHz, the

RAM requires an access time better than 75 ns.

Shared RAM Interface Signal Descriptions

Pin Name

Direction

Description

RA[16:0]

Output

The RAM address is provided by these pins. A maximum address size of 128K words is supported.

RD[15:0]

Bidirectional

The RAM data is provided on these pins. Word or byte operations are supported. When the shared memory

is not in use the data bus is output to prevent a floating data bus consuming power.

RCELN

Output

When asserted, a low byte (or word) shared RAM cycle is active.

RCEHN

Output

When asserted, a high byte (or word) shared RAM cycle is active.

RWRN

Output

When asserted, a write cycle is required. When deasserted a read cycle is required. This signal remains valid

before and while RCELN and RCEHN are asserted.