AD7683

Rev. 0 | Page 12 of 16

APPLICATION INFORMATION

SW+

MSB

16,384C

+IN

LSB

COMP

CONTROL

LOGIC

SWITCHES CONTROL

BUSY

OUTPUT CODE

CNV

REF

GND

–IN

4C

2C

C

C

32,768C

SW–

MSB

16,384C

LSB

4C

2C

C

C

32,768C

Figure 20. ADC Simplified Schematic

CIRCUIT INFORMATION

The AD7683 is a low power, single-supply, 16-bit ADC using a

successive approximation architecture.

The AD7683 is capable of converting 100,000 samples per sec-

ond (100 kSPS) and powers down between conversions. When

operating at 10 kSPS, for example, it consumes typically 150 µW

with a 2.7 V supply, ideal for battery-powered applications.

The AD7683 provides the user with an on-chip track-and-hold

and does not exhibit any pipeline delay or latency, making it

ideal for multiple, multiplexed channel applications.

The AD7683 is specified from 2.7 V to 5.5 V. It is housed in a

8-lead MSOP package or a tiny, 8-lead QFN (LFCSP) package.

The AD7683 is an improved second source to the ADS8320 and

ADS8325. For even better performance, consider the AD7685.

CONVERTER OPERATION

The AD7683 is a successive approximation ADC based on a

charge redistribution DAC. Figure 20 shows the simplified

schematic of the ADC. The capacitive DAC consists of two

identical arrays of 16 binary-weighted capacitors, which are

connected to the two comparator inputs.

During the acquisition phase, terminals of the array tied to the

comparator’s input are connected to GND via SW+ and SW−.

All independent switches are connected to the analog inputs.

Thus, the capacitor arrays are used as sampling capacitors and

acquire the analog signal on the +IN and −IN inputs. When the

acquisition phase is complete and the CS input goes low, a con-

version phase is initiated. When the conversion phase begins,

SW+ and SW− are opened first. The two capacitor arrays are

then disconnected from the inputs and connected to the GND

input. Therefore, the differential voltage between the inputs,

+IN and −IN, captured at the end of the acquisition phase is

applied to the comparator inputs, causing the comparator to

become unbalanced. By switching each element of the capacitor

array between GND and REF, the comparator input varies by

control logic toggles these switches, starting with the MSB, to

bring the comparator back into a balanced condition. After the

completion of this process, the part returns to the acquisition

phase and the control logic generates the ADC output code.

TRANSFER FUNCTIONS

The ideal transfer function for the AD7683 is shown in

Figure 21 and Table 8.

000...000

000...001

000...010

111...101

111...110

111...111

ANALOG INPUT

+FS – 1.5 LSB

+

FS – 1 LSB

–FS + 1 LSB

–FS

–FS + 0.5 LSB

Figure 21. ADC Ideal Transfer Function

Table 8. Output Codes and Ideal Input Voltages

Description

Analog Input

Digital Output Code

Hexadecimal

FSR – 1 LSB

4.999924 V

FFFF1

Midscale + 1 LSB

2.500076 V

8001

Midscale

2.5 V

8000

Midscale – 1 LSB

2.499924 V

7FFF

–FSR + 1 LSB

76.3 µV

0001

–FSR

0 V

00002