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FR9765 Datasheet(PDF) 10 Page - Fitipower Integrated Technology Inc. |
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FR9765 Datasheet(HTML) 10 Page - Fitipower Integrated Technology Inc. |
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10 / 11 page ![]() 10 FR9765-1.0-MAR-2012 FR9765 85T fitipower integrated technology lnc. Application Information (Continued) I=0.3 IO T(MA VIN VO T VO T FOSC I VIN Where VIN is the maximum input voltage. Compensation Components Selection FR9765 COMP C5 R3 Select the appropriate compensation value by following procedure: 1. Calculate the R4 value with the following equation: R4 2 CO T 0.1 FOSC VO T G A GCS VR F where GEA is the error amplifier voltage gain, and GCS is the current sense gain. 2. Calculate the C5 value with the following equation: C 4 2 R4 0.1 FOSC External Boost Diode Selection For 5V input or 5V output applications, it is recommended to add an external boost diode. This helps improving efficiency. The boost diode can be a low cost one, such as 1N4148. FR9765 VIN BS VIN SW D2 1N4148 5V C4 This diode is also recommended for high duty cycle operation (when duty cycle > 65%) and high output voltage (VOUT > 12V) applications. PCB Layout Recommendation The device’s performance and stability are dramatically affected by PCB layout. It is recommended to follow these general guidelines shown as below: 1. Place the input capacitors and output capacitors as close to the device as possible. The traces which connect to these capacitors should be as short and wide as possible to minimize parasitic inductance and resistance. 2. Place VIN bypass capacitors close to the VIN pin. 3. Place feedback resistors close to the FB pin. 4. Place compensation components close to the COMP pin. 5. Keep the sensitive signal (FB, COMP) away from the switching signal (SW). 6. The exposed pad of the package should be soldered to an equivalent area of metal on the PCB. This area should connect to the GND plane and have multiple via connections to the back of the PCB as well as connections to intermediate PCB layers. The GND plane area which connects to the exposed pad should be maximized to improve thermal performance. 7. Multi-layer PCB design is recommended. VIN VOUT SW 1 2 3 4 5 6 7 8 C4 L1 GND C2 C1 R2 R1 C6 Exposed Pad D1 Figure 15. Block Diagram of FR9765 |
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