Electronic Components Datasheet Search
  English  ▼

X  

MSM9810 Datasheet(PDF) 18 Page - OKI electronic componets

Part # MSM9810
Description  8-channel Mixing OKI ADPCM Type Voice Synthesis LSI
PDF  32 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  OKI [OKI electronic componets]
Direct Link  http://www.oki.com
Logo OKI - OKI electronic componets

MSM9810 Datasheet(HTML) 18 Page - OKI electronic componets

Back Button MSM9810 Datasheet HTML 14Page - OKI electronic componets MSM9810 Datasheet HTML 15Page - OKI electronic componets MSM9810 Datasheet HTML 16Page - OKI electronic componets MSM9810 Datasheet HTML 17Page - OKI electronic componets MSM9810 Datasheet HTML 18Page - OKI electronic componets MSM9810 Datasheet HTML 19Page - OKI electronic componets MSM9810 Datasheet HTML 20Page - OKI electronic componets MSM9810 Datasheet HTML 21Page - OKI electronic componets MSM9810 Datasheet HTML 22Page - OKI electronic componets Next Button
Zoom Inzoom in Zoom Outzoom out
 18 / 32 page
background image
18/31
¡ Semiconductor
MSM9810
8. Channel Status
The channel status is output from D7-D0.
There are two types of signals to be output as channel status: BUSYn (n = 1-8) signals and NCRn
signals. These two types are selected by the NCR/BUSY pin. When the NCR/BUSY pin is at “H”
level, NCR is output, and when at “L” level, BUSY is output.
The NCR signal is the command and subcommand input status signal (Next Command Request)
of each channel, and the WR signal input is enabled at “H” level.
The BUSY signal outputs “L” level while each channel is executing voice synthesis.
Each channel status signal is output from D7-D0 pins in parallel input interface, and from D5/
S0 pins and D3/SR3-D0/SR0 pins in serial input interface by control of RD. Table 8-1 shows the
relationship between D7-D0 and channels, and Figure 8-1 shows read timing in the parallel input
interface.
Table 8-1 Correspondence between D7-D0 and channels
Data bus
Corresponding channel
D7
D6
D5
D4
D3
D2
D1
D0
CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
tDRE
tRR
Data out Valid
RD(I)
D7 - D0(I/O)
tDRF
Figure 8-1 Read timing in parallel input interface
In serial input interface, serial output from D5/SO pins by control of CS and RD, and D3/SR3-
D0/SR0 parallel output (constantly output) can be selected.
For serial output from D5/SO pin, D7-D0, shown in Table 8-1, are output from MSB in serial at
the rise of the SI pin when the RD pin is at “L” level.
Figure 8-2 shows this timing.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com