GPCE040A datasheet(8/26 Pages) GENERALPLUS

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GPCE040A

Proprietary & Confidential

Oct 01, 2013

Version: 1.4

6.5. Low Voltage Detection and Low Voltage Reset

6.5.1. Low voltage detection (LVD)

The Low Voltage Detection (LVD) reports the circumstance of

present voltage.

There are three LVD levels to be selected: 2.5V,

2.9V, and 3.3V.

These levels can be programmed via

Port_LVD_Ctrl (W).

As an example, suppose LVD is given to

2.9V.

When the voltage drops below 2.9V, the b15 of

Port_LVD_Ctrl is read as HIGH.

In such state, program can be

designed to react to this condition.

6.5.2. Low voltage reset

In addition to the LVD, the GPCE040A has another important

function, Low Voltage Reset (LVR).

With the LVR function, a

reset signal is generated to reset system when the operating

voltage drops below 2.3V for 10 consecutive CPU clock cycles.

Without LVR, the CPU becomes unstable and malfunctions when

the operating voltage drops below 2.3V.

The LVR will reset all

functions to the initial operational (stable) states when the voltage

drops below 2.3V.

A LVR timing diagram is given as follows:

2.3V

VDD

CPU

Tvdd

Tw=F

CPU x 10 cycle

Tvdd > Tw

Treset

RESET

Treset = F

CPU x512 cycle

6.6. Interrupt

The GPCE040A has 14 interrupt sources, grouped into two types,

FIQ (Fast Interrupt Request) and IRQ (Interrupt request).

The

priority of FIQ is higher than IRQ.

FIQ is the high-priority interrupt

while IRQ is the low-priority one.

An IRQ can be interrupted by a

FIQ, but not by another IRQ.

A FIQ cannot be interrupted by any

other interrupt sources.

Interrupt Source

Interrupt Name

Priority

Fosc/1024

FIQ_PWM/IRQ0_PWM

High(FIQ)

Timer A

FIQ_TMA/ IRQ1_TMA

High(FIQ)

Timer B

FIQ_TMB/ IRQ2_TMB

High(FIQ)

Interrupt Source

Interrupt Name

Priority

EXT2

IRQ3_EXT2

Low

EXT1

IRQ3_EXT1

Low

Key change wakeup

IRQ3_KEY

Low

4096Hz

IRQ4_4KHz

Low

2048Hz

IRQ4_2KHZ

Low

1024Hz

IRQ4_1KHz

Low

4Hz

IRQ5_4Hz

Low

2Hz

IRQ5_2Hz

Low

Time-base 1

IRQ6_TMB1

Low

Time-base 2

IRQ6_TMB2

Low

UART (TxRDY or RxRDY)

UART IRQ

Low

6.7. I/O

Two I/O ports are built in GPCE040A, PortA and PortB.

The

PortA is an ordinary I/O with programmable wakeup capability.

addition to the regular IO function, the PortB can also perform

some special functions in certain pins.

Suppose operating

voltage is running at 3.6V (VDD) and VDDIO (power for I/O)

operates from 3.6V (VDD) to 5.5V.

In such condition, the I/O pad

is capable of operating from 0V through VDDIO.

The following

diagram is an I/O schematic.

Control

logic

pull high

pull low

Pin pad

Buffer(R)

Data(R)

Port_Data(W)

Port_Buffer(W)

Port_DIR(R/W)

Port_ATTR(R/W)

Although data can be written into the same register through

Port_Data and Port_Buffer, they can be read from different places,

Buffer (R) and Data (R).

The IOA [7:0] is the key wakeup port.

To activate key wakeup function, latch data on PORT_IOA_Latch

and enable the key wakeup function.

Wakeup is triggered when

the PortA state is different from at the time latched.

In addition to

an ordinary I/O port, PortB carries some special functions.

summary of PortB special functions is listed as follows:

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