HSP3824 datasheet(13/41 Pages) HARRIS

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HSP3824

Deﬁnitions

Normal - Device in the full protocol mode (Mode 3).

TXCLK - Transmit clock (PN rate).

Initial Detect - Indicates that Signal Quality 1 and 2 (SQ1

and SQ2) exceed their programmed thresholds. Signal qual-

ities are a function of phase error and correlator magnitude

outputs.

ED - energy detect indicates that the RSSI value exceeds its

programmed threshold.

CRS - indicates that a signal has been acquired (PN acquisi-

tion).

Mag - Magnitude output from the correlator.

DCLK - Data symbol clock.

FrqReg - Contents of the NCO frequency register.

Phase - phase of signal after carrier loop correction.

NCO PhaseAccumReg - Contents of the NCO phase accu-

mulation register.

LoadSQ - Strobe that samples and updates Signal Quality,

SQ1 and SQ2 values.

SQ2 - Signal Quality measure #2. Signal phase variance

after removal of data, 8 MSBs of most recent 16-bit stored

value.

RXCLK - Receive clock (RX sample clock). Nominally 22MHz.

BitSyncAccum - Real time monitor of the bit synchroniza-

tion accumulator contents, mantissa only.

SQ1 - Signal Quality measure #1. Contents of the bit sync

accumulator 8 MSBs of most recent 16-bit stored value.

A/D_Cal_ck - Clock for applying A/D calibration corrections.

ADCal - 5-bit value that drives the D/A adjusting the A/D ref-

erence.

External AGC Control

The ADC cal output (pin 26) is a binary signal that ﬂuctuates

between logic levels as the signals in the I and Q channels

are either at full scale or not. If the input level is too high, this

output will have a higher duty cycle, and visa versa. Thus,

this signal could be integrated with an R-C ﬁlter to develop

an AGC control voltage. The AGC feedback should be

designed to drive it to 50% duty cycle. In the case that an

external AGC is in use then the ADC calibration circuit must

not be programmed for automatic level adjustment.

Power Down Modes

The power consumption modes of the HSP3824 are con-

trolled by the following control signals.

Receiver Power Enable (RX_PE,pin 33), which disables the

receiver when inactive.

Transmitter Power Enable (TX_PE, pin 2), which disables the

transmitter when inactive.

Reset (RESET, pin 28), which puts the receiver in a sleep

mode when it is asserted at least 2 MCLKs after RX_PE is

set at its inactive state. The power down mode where, both

RESET and RX_PE are used is the lowest possible power

consumption mode for the receiver. Exiting this mode

requires a maximum of 10

µs before the device is back at its

operational mode.

The contents of the Conﬁguration Registers is not effected

by any of the power down modes. The external processor

does not have access and cannot modify any of the CRs

during the power down modes. No reconﬁguration is

required when returning to operational modes.

Table 6 describes the power down modes available for the

HSP3824 (VCC = 5.0V). The table values assume that all

other inputs to the part (MCLK, SCLK, etc.) continue to run.

A/D Cal Test

Mode

A/D

CAL_CK

CRS, ED, “0”, ADCal (4:0)

Reserved

(0Ah)

Reserved

TABLE 5. TEST MODES (Continued)

MODE

DESCRIPTION

TEST_CLK

TEST (7:0)

TABLE 6. POWER DOWN MODES

RX_PE

TX_PE

RESET

POWER

(22MHz)

POWER

(44MHz)

DEVICE STATE

Inactive

Active

40mW

100mW

Both transmit and receive functions disabled. Device in sleep

mode. Control Interface is still active. Register values are main-

tained. Device will return to its active state within 10

µs.

Inactive

325mW

475mW

Both transmit and receive operations disabled. Device will become

in its active state within 1

µs.

Inactive

Active

Inactive

335mW

500mW

Receiver operations disabled. Receiver will return in its active state

within 1

µs.

Active

Inactive

335mW

500mW

Transmitter operations disabled. Transmitter will return to its active

state within 2 MCLKs.

Active

340mW

525mW

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