2

AT76C712

5635AS–USB–12/04

Overview

Atmel’s AT76C712 is a low-power USB peripheral that can connect various types of

devices to a common USB port.

•

The device is based on the AVR-enhanced RISC architecture core, which combines

an advanced instruction set with 32 general-purpose working registers. By

executing powerful instructions in a single clock cycle, the AT76C712 achieves

throughputs approaching 1MIPS per MHz, allowing the system designer to optimize

power consumption versus processing speed

•

The clock generation circuit requires a clock input of 12 MHz and provides standard

clock rates for the USB module and the on-chip UARTs, as well as several AVR

CPU rates varying from 16 MHz up to 48 MHz

•

Internal DMA channels allow fast data transfers between the USB buffers and the

external and on-chip memory without processor interruption. USB DMA transfers

use devoted data paths with a 12 Mbytes transfer rate

•

An on-chip flexible memory controller allows dynamic memory mapping and

provides the required timing for interfacing with slow or fast external memory

devices, like SRAM or FIFOs

•

Twenty-five multipurpose I/O pins provide the signals for the external interfaces. The

device also offers two external interrupts, a programmable Watchdog Timer, flexible

timer/counters with compare modes, and the support of various power-down modes

•

On power-up, the bootstrap code is executed from the boot ROM. The purpose of

the bootstrap code is to load the application code into the program memory. The

application code is executed from the on-chip SRAM program memory contributing

to the low-power consumption. Different programming modes are supported

depending on the application (that is, the mode is selected externally by the

PMODE0 and PMODE1 pins)

•

In the slave programming mode, an external system (that is, the Host), operating as

SPI master, can transfer the program image in a raw format to the program memory

of the device. In this case, the device operates as an SPI slave and starts running

from the internal boot ROM code, which switches to the start of program memory

when it detects the end of a valid program transfer from the Host to the AT76C712

(see the “Slave Programmming Mode” on page 9)

•

In a master programming mode, the AT76C712 reads the whole program image

from an external SPI EEPROM or DataFlash and switches to the start of program

memory when it completes the reading (see the “Master Programming Modes” on

page 10). Alternatively, the AT76C712 reads only configuration parameters from a

small serial non-volatile memory (EEPROM or DataFlash), enables the USB

Controller, and executes the USB Device Firmware Upgrade (DFU) code that is

stored in the boot ROM

•

The USB Controller consists of a Serial Interface Engine (SIE), a Function Interface

Unit (FIU), and a System Interface (SI). The SIE performs bit processing, line

coding, packet generation and packet type recognition, serial-parallel data

conversion, and packet delineation. The FIU consists of a protocol engine and a

USB device with one Control Endpoint (EP0) and seven programmable Endpoints

with up to 512 bytes maximum total size. All Endpoints support double buffering in

order to provide the maximum performance specified for the USB

•

The device supports two 16550 UART modules with 16 bytes FIFOs in each

direction. UART0 serial interface provides full modem control functionality with the

RTS/CTS, DTR/DSR, RI, and CD signals. These signals are provided by the

general-purpose I/O pins of PORTD