GS3471 datasheet(110/179 Pages) SEMTECH

110 / 179 page

GS3471

Final Data Sheet Rev.4

PDS-060498

September 2017

110 of 179

Semtech

www.semtech.com

Table 5-6: Equalizer Registers

Function

GSPI Addressh

Equalizer Configuration 0

EQ_CONF_REG_0

Equalizer Configuration 1

EQ_CONF_REG_1

Equalizer Configuration 2

EQ_CONF_REG_2

Output Configuration 0

OUT_CONF_REG_0

Output Configuration 1

OUT_CONF_REG_1

Status Register

STATUS_REG_0

EQ LOS Filter Configuration

EQ_LOS_FILTER_

CONF_REG_0

LOS Filter Configuration

LOS_FILTER_ CONF_REG_1

Internal Source

Configuration

INT_OUT_ CONF_REG_0

Reset Register

RESET_REG_0

Table 5-7: Glossary of Terms

Term

Description

Read-write

Read-only

Write-only

ROCW1

Read-only, clear on write

ROCR

Read-only, clear on read

RSVD2

Read, modify, write

Note:

1) For each bit in the register that needs to be cleared, write 1.



If all bits in the register need to be cleared, write FFFFh.

2) To modify a bit in a register that has other bits marked RSVD, read

the existing value, modify only the non-reserved bits and then write

the final value. For example, to change bit 9 in register 989h, a read

would produce 0000h, modify to 0200h and write 0200h.

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