AW2015 datasheet(13/35 Pages) AWINIC

13 / 35 page

AW2015,AW2015A

Step. 2017 V1.3

www.awinic.com.cn

Master sends control register address (8-bit)

Slave sends acknowledge signal

Master sends data byte to be written to the addressed register

Slave sends acknowledge signal

If master will send further data bytes the control register address will be incremented by one after

acknowledge signal (repeat step 6,7)

Master generates STOP condition to indicate write cycle end

A2 A1 A0

A6 A5

A4 A3

D5 D4

D1 D0

SCL

SDA

Ack

Start

R/W

Stop

Device Address

Write Data

Ack

Figure 6. I2C Write Byte Cycle

Read Cycle

In a read cycle, the following steps should be followed:

Master device generates START condition

Master device sends slave address (7-bit) and the data direction bit (r/w = 0).

Slave device sends acknowledge signal if the slave address is correct.

Master sends control register address (8-bit)

Slave sends acknowledge signal

Master generates STOP condition followed with START condition or REPEAT START condition

Master device sends slave address (7-bit) and the data direction bit (r/w = 1).

Slave device sends acknowledge signal if the slave address is correct.

Slave sends data byte from addressed register.

If the master device sends acknowledge signal, the slave device will increase the control register

address by one, then send the next data from the new addressed register.

If the master device generates STOP condition, the read cycle is ended.

AW2015 Datasheet(PDF) 13 Page - Shanghai awinic technology co.,ltd