DS2764 High-Precision Li+ Battery Monitor With 2-Wire Interface

15 of 20

CC—CC Pin Mirror. This read-only bit mirrors the state of the CC output pin.

DC—DC Pin Mirror. This read-only bit mirrors the state of the DC output pin.

CE—Charge Enable. Writing a 0 to this bit disables charging (

CC output high, external charge FET off) regardless

of cell or pack conditions. Writing a 1 to this bit enables charging, subject to override by the presence of any

protection conditions. The DS2764 automatically sets this bit to 1 when it transitions from sleep mode to active

mode.

DE—Discharge Enable. Writing a 0 to this bit disables discharging (

DC output high, external discharge FET off)

regardless of cell or pack conditions. Writing a 1 to this bit enables discharging, subject to override by the presence

of any protection conditions. The DS2764 automatically sets this bit to 1 when it transitions from sleep mode to

active mode.

STATUS REGISTER

The read-only Status register shows the status of bits which enable or disable selected functions of the DS2764.

Functions are enabled or disabled by programming a default value for the corresponding bits in lockable EEPROM

address 31h. After writing the desired value to 31h, the Copy Data and Recall Data commands for EEPROM block

1 are required to transfer the default values into the status register bits and activate the selected functions. The

selected functions become the default mode of the DS2764 since a recall from block 1 occurs on power-up. The

format of the Status register is shown in Figure 12.

Figure 12. Status Register Format

ADDRESS 01

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

X

X

PMOD

X

X

X

X

X

X—Reserved Bits.

PMOD—Sleep Mode Enable. A value of 1 in this bit enables the DS2764 to enter sleep mode when the bus is low

for greater than 2s and to leave sleep mode when the SCL OR SDA line goes high. A value of 0 disables bus-

related transitions into and out of sleep mode. This bit is read-only. The desired default value should be set in bit 5

of address 31h. The factory default is 0.

EEPROM REGISTER

The format of the EEPROM register is shown in Figure 13. The function of each bit is described in detail in the

following paragraphs.

Figure 13. EEPROM Register Format

ADDRESS 07

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

EEC

LOCK

X

X

X

BL2

BL1

BL0

EEC—EEPROM Copy Flag. A 1 in this read-only bit indicates that a Copy Data or Lock function command is in

progress. While this bit is high, writes to EEPROM addresses are ignored and Copy Data and Lock function

commands cannot be issued. A 0 in this bit indicates that data may be written to unlocked EEPROM blocks.

LOCK—EEPROM Lock Enable. When this bit is 0, the Lock function command is ignored. Writing a 1 to this bit

enables the Lock function command. After the Lock function command is executed, the LOCK bit is reset to 0. The

factory default is 0.