MAX31342 datasheet(4/24 Pages) MAXIM

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Electrical Characteristics (continued)

(VCC = +1.6V to +3.6V, typical values at VCC = +3.0V, unless otherwise noted. Limits are 100% tested at TA = +25°C, unless

otherwise noted. Limits over the operating temperature range, and relevant supply voltage range, are guaranteed by design and

characterization (Note 1).)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Data Setup Time

tSU:DAT

VCC = 3V. (Note 8)

100

Setup Time for a

Repeated, START

Condition

tSU:STA

0.6

µs

Minimum Rise Time of

Both SDA and SCL

Signals

(Note 9)

20 +

0.1CB

Maximum Rise Time of

Both SDA and SCL

Signals

300

Minimum Fall Time for

Both SDA and SCL

Signals

(Note 9)

20 +

0.1CB

Maximum Fall Time for

Both SDA and SCL

Signals

300

Setup Time for STOP

Condition

tSU:STO

0.6

µs

Maximum Capacitive

Load for Each Bus Line

(Note 9)

400

I/O Capacitance

CI/O

SCL Spike Suppression

tSP

Oscillator Stop Flag

(OSF) Delay

tOSF

(Note 11)

100

Timeout Interval

tTIMEOUT

(Note 12)

Note 1:

Limits at -40°C and 85°C are guaranteed by design; not production tested.

Note 2:

Voltage referenced to ground.

Note 3:

Specified with I2C bus inactive. Oscillator operational.

Note 4:

The minimum SCL clock frequency is limited by the bus timeout feature, which resets the serial bus interface if SCL is held

low for tTIMEOUT.

Note 5:

After this period, the first clock pulse is generated.

Note 6:

A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal)

to bridge the undefined region of the falling edge of SCL.

Note 7:

The maximum tHD:DAT need only be met if the device does not stretch the low period (tLOW) of the SCL signal.

Note 8:

A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ to 250ns must then be met. This

is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low

period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000 + 250 = 1250ns before the

SCL line is released.

Note 9:

CB is the total capacitance of one bus line, including all connected devices, in pF.

Note 10: Guaranteed by design; not 100% production tested.

Note 11: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of

2.4V ≤ VCC ≤ VCCMAX.

Note 12: The MAX31342 can detect the SCL clock low signal longer than the tTIMEOUT. When this occurs, the device I2C interface is

in reset state. Once the device detects a START condition where SCL is held low shorter than tTIMEOUT, it exits out of reset

and SDA output is released. The oscillator must be running for this function to work.

MAX31342

Low-Current, Real-Time Clock with I2C Interface

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