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AM5728 Datasheet(PDF) 183 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 183 Page - Texas Instruments |
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183 / 415 page  183 AM5729, AM5728, AM5726 www.ti.com SPRS953F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 Specifications Copyright © 2015–2019, Texas Instruments Incorporated Table 5-10. LVCMOS DDR DC Electrical Characteristics PARAMETER MIN NOM MAX UNIT Signal Names in MUXMODE 0 (Single-Ended Signals): ddr1_d[31:0], ddr1_a[15:0], ddr1_dqm[3:0], ddr1_ba[2:0], ddr1_csn[0], ddr1_cke, ddr1_odt[0], ddr1_casn, ddr1_rasn, ddr1_wen, ddr1_rst, ddr1_ecc_d[7:0], ddr1_dqm_ecc, ddr2_d[31:0], ddr2_a[15:0], ddr2_dqm[3:0], ddr2_ba[2:0], ddr2_csn[0], ddr2_cke, ddr2_odt[0], ddr2_casn, ddr2_rasn, ddr2_wen, ddr2_rst; Balls: AA28 / AA25 / AA26 / Y24 / AA24 / Y23 / Y22 / AA23 / Y20 / AB27 / Y19 / AC27 / AC28 / AB28 / W20 / V20 / AD25 / AC24 / AC25 / AE26 / AF28 / AG27 / AF27 / AC23 / AE23 / AF23 / AE24 / AF24 / AH26 / AG26 / AF26 / AF25 / AD18 / AE17 / AF18 / AC21 / AD22 / AD21 / AE22 / AF22 / AE21 / AE21 / AH22 / AF21 / AB19 / AC20 / AC19 / AD20 / AA27 / AC26 / AB23 / AD23 / AB18 / AE18 / AF17 / AH23 / AG22 / AE20 / AC18 / AF20 / AH21 / AG21 / Y26 / V25 / V24 / Y25 / W23 / W19 / V23 / W22 / V26 / M26 / M25 / M24 / M23 / L28 / L25 / L26 / L27 / J20 / K22 / J23 / L24 / L23 / K21 / K20 / L22 / J24 / J26 / J25 / G26 / H26 / H24 / H25 / H23 / E28 / E27 / F27 / F26 / F24 / F25 / G25 / E26 / U22 / R22 / T22 / N28 / P26 / N23 / N27 / P27 / N20 / P25 / P22 / P23 / R27 / R28 / R26 / R25 / M22 / K23 / G24 / F28 / U26 / U27 / U23 / P24 / U24 / R23 / U28 / T23 / U25 / R24; Driver Mode VOH High-level output threshold (IOH = 0.1 mA) 0.9*VDDS V VOL Low-level output threshold (IOL = 0.1 mA) 0.1*VDDS V CPAD Pad capacitance (including package capacitance) 3 pF ZO Output impedance (drive strength) l[2:0] = 000 (Imp80) 80 Ω l[2:0] = 001 (Imp60) 60 l[2:0] = 010 (Imp48) 48 l[2:0] = 011 (Imp40) 40 l[2:0] = 100 (Imp34) 34 Single-Ended Receiver Mode VIH High-level input threshold DDR3/DDR3L VREF+0.1 VDDS+0.2 V VIL Low-level input threshold DDR3/DDR3L -0.2 VREF-0.1 V VCM Input common-mode voltage VREF -10%vdds VREF+ 10%vdds V CPAD Pad capacitance (including package capacitance) 3 pF Signal Names in MUXMODE 0 (Differential Signals): ddr1_dqs[3:0], ddr1_dqsn[3:0], ddr1_ck, ddr1_nck, ddr2_dqs[3:0], ddr2_dqsn[3:0], ddr2_ck, ddr2_nck, ddr1_dqs_ecc, ddr1_dqsn_ecc; Bottom Balls: Y28 / AD27 / AE27 / AH25 / Y27 / AD28 / AE28 / AG25 / AG24 / AH24 / M28 / K27 / H27 / G28 / M27 / K28 / H28 / G27 / T28 / T27 / V27 / V28; Driver Mode VOH High-level output threshold (IOH = 0.1 mA) 0.9*VDDS V VOL Low-level output threshold (IOL = 0.1 mA) 0.1*VDDS V CPAD Pad capacitance (including package capacitance) 3 pF ZO Output impedance (drive strength) l[2:0] = 000 (Imp80) 80 Ω l[2:0] = 001 (Imp60) 60 l[2:0] = 010 (Imp48) 48 l[2:0] = 011 (Imp40) 40 l[2:0] = 100 (Imp34) 34 Single-Ended Receiver Mode VIH High-level input threshold DDR3/DDR3L VREF+0.1 VDDS+0.2 V VIL Low-level input threshold DDR3/DDR3L -0.2 VREF-0.1 V VCM Input common-mode voltage VREF -10%vdds VREF+ 10%vdds V CPAD Pad capacitance (including package capacitance) 3 pF |
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