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AM5728 Datasheet(PDF) 204 Page - Texas Instruments

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Part # AM5728
Description  Sitara Processors Silicon Revision 2.0
PDF  415 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

AM5728 Datasheet(HTML) 204 Page - Texas Instruments

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xi_osc1
CK0
CK1
CK1
204
AM5729, AM5728, AM5726
SPRS953F – DECEMBER 2015 – REVISED MAY 2019
www.ti.com
Submit Documentation Feedback
Product Folder Links: AM5729 AM5728 AM5726
Clock Specifications
Copyright © 2015–2019, Texas Instruments Incorporated
(1) To switch from bypass mode to crystal or from crystal mode to bypass mode, there is a waiting time about 100 μs; however, if the chip
comes from bypass mode to crystal mode the crystal will start-up after time mentioned in Table 6-6, tsX parameter.
(2) Before the processor boots up and the oscillator is set to bypass mode, there is a waiting time when the internal oscillator is in
application mode and receives a wave. The switching time in this case is about 100 μs.
Table 6-8 details the OSC1 input clock timing requirements.
Table 6-8. OSC1 Input Clock Timing Requirements
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
CK0
1 /
tc(xiosc1)
Frequency, xi_osc1
Range from 12 to 38.4
MHz
CK1
tw(xiosc1)
Pulse duration, xi_osc1 low or high
0.45 *
tc(xiosc1)
0.55 *
tc(xiosc1)
ns
tj(xiosc1)
Period jitter(1), xi_osc1
0.01 ×
tc(xiosc1)
(3)
ns
tR(xiosc1)
Rise time, xi_osc1
5
ns
tF(xiosc1)
Fall time, xi_osc1
5
ns
tj(xiosc1)
Frequency accuracy(2), xi_osc1
Ethernet not used
±200
ppm
Ethernet RGMII and RMII
using derived clock
±50
Ethernet MII using derived
clock
±100
(1) Period jitter is meant here as follows:
–
The maximum value is the difference between the longest measured clock period and the expected clock period
–
The minimum value is the difference between the shortest measured clock period and the expected clock period
(2) Crystal characteristics should account for tolerance+stability+aging.
(3) The Period jitter requirement for osc1 can be relaxed to 0.02*tc(xiosc1) under the following constraints:
a.The osc1/SYS_CLK2 clock bypasses all device PLLs
b.The osc1/SYS_CLK2 clock is only used to source the DSS pixel clock outputs
Figure 6-9. xi_osc1 Input Clock
6.1.4
RTC Oscillator Input Clock
FUNC_32K_CLK is received directly from RTC Oscillator. For more information about FUNC_32K_CLK
see Device TRM, Chapter: Power, Reset, and Clock Management.
NOTE
RTC only mode is not supported feature.
6.1.4.1
RTC Oscillator External Crystal
An external crystal is connected to the device pins. Figure 6-10 describes the crystal implementation.



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