AM5728 datasheet(208/415 Pages) TI1

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AM5729, AM5728, AM5726

SPRS953F – DECEMBER 2015 – REVISED MAY 2019

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Clock Specifications

NOTE

For more information for not controlled from PRCM DPLL’s see the related chapters in TRM.

6.3.1

DPLL Characteristics

The DPLL has three relevant input clocks. One of them is the reference clock (CLKINP) used to generated

the synthesized clock but can also be used as the bypass clock whenever the DPLL enters a bypass

mode. It is therefore mandatory. The second one is a fast bypass clock (CLKINPULOW) used when

selected as the bypass clock and is optional. The third clock (CLKINPHIF) is explained in the next

paragraph.

The DPLL has three output clocks (namely CLKOUT, CLKOUTX2, and CLKOUTHIF). CLKOUT and

CLKOUTX2 run at the bypass frequency whenever the DPLL enters a bypass mode. Both of them are

generated from the lock frequency divided by a post-divider (namely M2 post-divider). The third clock,

CLKOUTHIF, has no automatic bypass capability. It is an output of a post-divider (M3 post-divider) with

the input clock selectable between the internal lock clock (Fdpll) and CLKINPHIF input of the PLL through

an asynchronous multplexing.

For more information, see the Power, Reset, and Clock Management chapter of the Device TRM.

Table 6-12 summarizes DPLL type described in Section 6.3, DPLLs, DLLs Specifications introduction.

Table 6-12. DPLL Control Type

DPLL NAME

TYPE

CONTROLLED BY PRCM

DPLL_ABE

Table 6-13 (Type A)

Yes(1)

DPLL_CORE

Table 6-13 (Type A)

Yes(1)

DPLL_DEBUGSS

Table 6-13 (Type A)

No(2)

DPLL_DSP

Table 6-13 (Type A)

Yes(1)

DPLL_GMAC

Table 6-13 (Type A)

Yes(1)

DPLL_HDMI

Table 6-14 (Type B)

No(2)

DPLL_IVA

Table 6-13 (Type A)

Yes(1)

DPLL_MPU

Table 6-13 (Type A)

Yes(1)

DPLL_PER

Table 6-13 (Type A)

Yes(1)

APLL_PCIE

Table 6-13 (Type A)

Yes(1)

DPLL_PCIE_REF

Table 6-14 (Type B)

Yes(1)

DPLL_SATA

Table 6-14 (Type B)

No(2)

DPLL_USB

Table 6-14 (Type B)

Yes(1)

DPLL_USB_OTG_SS

Table 6-14 (Type B)

No(2)

DPLL_VIDEO1

Table 6-13 (Type A)

No(2)

DPLL_VIDEO2

Table 6-13 (Type A)

No(2)

DPLL_DDR

Table 6-13 (Type A)

Yes(1)

DPLL_GPU

Table 6-13 (Type A)

Yes(1)

(1) DPLL is in the always-on domain.

(2) DPLL is not controlled by the PRCM.

Table 6-13 and Table 6-14 summarize the DPLL characteristics and assume testing over recommended

operating conditions.

Table 6-13. DPLL Type A Characteristics

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

COMMENTS

finput

CLKINP input frequency

0.032

MHz

FINP

finternal

Internal reference frequency

0.15

MHz

REFCLK

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