AM5728 datasheet(210/415 Pages) TI1

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AM5729, AM5728, AM5726

SPRS953F – DECEMBER 2015 – REVISED MAY 2019

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Clock Specifications

Table 6-14. DPLL Type B Characteristics (continued)

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

COMMENTS

tlock

Frequency lock time

350 ×

REFCLKs

µs

plock

Phase lock time

500 ×

REFCLKs

µs

trelock-L

Relock time—Frequency lock(3)

(LP relock time from bypass)

9 + 30 ×

REFCLKs

µs

prelock-L

Relock time—Phase lock(3) (LP

relock time from bypass)

9 + 125 ×

REFCLKs

µs

(1) The minimum frequency on CLKOUT is assuming M2 = 1.

For M2 > 1, the minimum frequency on this clock will further scale down by factor of M2.

(2) The maximum frequency on CLKOUT is assuming M2 = 1.

(3) Relock time assumes typical operating conditions, 10°C maximum temperature drift.

(4) Bypass mode: fCLKOUT = FINP if ULOWCLKEN = 0. For more information, see the Device TRM.

(5) For output clocks, there are two frequency ranges according to the SELFREQDCO setting. For more information, see the Device TRM.

6.3.2

DLL Characteristics

Table 6-15 summarizes the DLL characteristics and assumes testing over recommended operating

conditions.

Table 6-15. DLL Characteristics

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

finput

Input clock frequency (EMIF_DLL_FCLK)

266

MHz

tlock

Lock time

50k

cycles

trelock

Relock time (a change of the DLL frequency implies that DLL must relock)

50k

cycles

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