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AM5728 Datasheet(PDF) 213 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 213 Page - Texas Instruments |
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213 / 415 page ![]() 213 AM5729, AM5728, AM5726 www.ti.com SPRS953F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns). 7.3.1.3 Timing Parameters and Board Routing Analysis The timing parameter values specified in this data manual do not include delays by board routes. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays. TI recommends using the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for timing Analysis application report (literature number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing differences. 7.4 Recommended Clock and Control Signal Transition Behavior All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic manner. Monotonic transitions are more easily ensured with faster switching signals. Slower input transitions are more susceptible to glitches due to noise and special care should be taken for slow input clocks. 7.5 Virtual and Manual I/O Timing Modes Some of the timings described in the following sections require the use of Virtual or Manual I/O Timing Modes. Table 7-2 provides a summary of the Virtual and Manual I/O Timing Modes across all device interfaces. The individual interface timing sections found later in this document provide the full description of each applicable Virtual and Manual I/O Timing Mode. Refer to the Pad Configuration section of the device TRM for the procedure on implementing the Virtual and Manual Timing Modes in a system. Table 7-2. Modes Summary Virtual or Manual IO Mode Name Data Manual Timing Mode VIP VIP1_MANUAL1 VIN1A/1B/2A Rise-Edge Capture Mode Timings VIP1_2B_MANUAL1 VIN2B Rise-Edge Capture Mode Timings VIP1_MANUAL2 VIN1A/1B/2A Fall-Edge Capture Mode Timings VIP1_2B_MANUAL2 VIN2B Fall-Edge Capture Mode Timings VIP2_MANUAL1 VIN3A, VIN3B IOSET1 Rise-Edge Capture Mode Timings VIP2_4A_MANUAL1 VIN4A IOSET1/2 Rise-Edge Capture Mode Timings VIP2_4A_IOSET3_MANUAL1 VIN4A IOSET3 Rise-Edge Capture Mode Timings VIP2_4B_MANUAL1 VIN4B Rise-Edge Capture Mode Timings VIP2_3B_IOSET2_MANUAL1 VIN3B IOSET2 Rise-Edge Capture Mode Timings VIP2_3B_IOSET2_MANUAL2 VIN3B IOSET2 Fall-Edge Capture Mode Timings VIP2_MANUAL2 VIN3A, VIN3B IOSET1, VIN4A IOSET1/2 Fall-Edge Capture Mode Timings VIP2_4A_MANUAL2 VIN4A IOSET1/2 Fall-Edge Capture Mode Timings VIP2_4A_IOSET3_MANUAL2 VIN4A IOSET3 Fall-Edge Capture Mode Timings VIP2_4B_MANUAL2 VIN4B Fall-Edge Capture Mode Timings VIP3_MANUAL1 VIN5A and VIN6A Rise-Edge Capture Mode Timings VIP3_MANUAL2 VIN5A and VIN6A Fall-Edge Capture Mode Timings DPI Video Output VOUT1_MANUAL1 DPI1 Video Output Alternate Timings VOUT1_MANUAL2 DPI1 Video Output Default Timings VOUT1_MANUAL3 DPI1 Video Output MANUAL3 Timings VOUT1_MANUAL4 DPI1 Video Output MANUAL4 Timings VOUT2_IOSET1_MANUAL1 DPI2 Video Output IOSET1 Alternate Timings VOUT2_IOSET1_MANUAL2 DPI2 Video Output IOSET1 Default Timings |
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