AM5728 datasheet(247/415 Pages) TI1

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AM5729, AM5728, AM5726

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SPRS953F – DECEMBER 2015 – REVISED MAY 2019

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Timing Requirements and Switching Characteristics

Table 7-25. GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - Default (continued)

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

F21

tsu(waitV-clkH)

Setup time, gpmc_wait[1:0] valid before gpmc_clk high

2.23

F22

th(clkH-waitV)

Hold Time, gpmc_wait[1:0] valid after gpmc_clk high

1.52

NOTE

Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of

wait monitoring feature, see General-Purpose Memory Controller section in the Device TRM.

Table 7-26. GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Default

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

tc(clk)

Cycle time, output clock gpmc_clk period

11.3

td(clkH-nCSV)

Delay time, gpmc_clk rising edge to gpmc_cs[7:0] transition

F-1.48(6)

F+3.84(6)

td(clkH-nCSIV)

Delay time, gpmc_clk rising edge to gpmc_cs[7:0] invalid

E-1.48(5)

E +3.84(5)

td(ADDV-clk)

Delay time, gpmc_a[27:0] address bus valid to gpmc_clk first edge

B-1.69(2)

B+3.76(2)

td(clkH-ADDIV)

Delay time, gpmc_clk rising edge to gpmc_a[27:0] gpmc address bus invalid

-1.69

td(nBEV-clk)

Delay time, gpmc_ben[1:0] valid to gpmc_clk rising edge

B-3.8(2)

B+2.37(2)

td(clkH-nBEIV)

Delay time, gpmc_clk rising edge to gpmc_ben[1:0] invalid

D-0.4(4)

D+1.1(4)

td(clkH-nADV)

Delay time, gpmc_clk rising edge to gpmc_advn_ale transition

G-1.48

(7)

G+3.84 (7)

td(clkH-nADVIV)

Delay time, gpmc_clk rising edge to gpmc_advn_ale invalid

D-1.48

(4)

G+3.84 (7)

F10

td(clkH-nOE)

Delay time, gpmc_clk rising edge to gpmc_oen_ren transition

H-1.41

(8)

H+2.45 (8)

F11

td(clkH-nOEIV)

Delay time, gpmc_clk rising edge to gpmc_oen_ren invalid

E-1.41

(5)

E+2.1 (5)

F14

td(clkH-nWE)

Delay time, gpmc_clk rising edge to gpmc_wen transition

I-1.18 (9)

I+3.68 (9)

F15

td(clkH-Data)

Delay time, gpmc_clk rising edge to gpmc_ad[15:0] data bus transition

J-1.89

(10)

J+4.89

(10)

F17

td(clkH-nBE)

Delay time, gpmc_clk rising edge to gpmc_ben[1:0] transition

J-1.3

(10)

J+3.8 (10)

F18

tw(nCSV)

Pulse duration, gpmc_cs[7:0] low

A (1)

F19

tw(nBEV)

Pulse duration, gpmc_ben[1:0] low

C (3)

F20

tw(nADVV)

Pulse duration, gpmc_advn_ale low

K (11)

F23

td(CLK-GPIO)

Delay time, gpmc_clk transition to gpio6_16.clkout1 transition

1.2

6.1

Table 7-27. GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - Alternate

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

F12

tsu(dV-clkH)

Setup time, read gpmc_ad[15:0] valid before gpmc_clk high

3.56

F13

th(clkH-dV)

Hold time, read gpmc_ad[15:0] valid after gpmc_clk high

1.9

F21

tsu(waitV-clkH)

Setup time, gpmc_wait[1:0] valid before gpmc_clk high

3.1

F22

th(clkH-waitV)

Hold Time, gpmc_wait[1:0] valid after gpmc_clk high

1.9

Table 7-28. GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Alternate

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

tc(clk)

Cycle time, output clock gpmc_clk period (12)

15.04

td(clkH-nCSV)

Delay time, gpmc_clk rising edge to gpmc_cs[7:0] transition

F-0.84 (6)

F+6.73

(6)

AM5728 Datasheet(PDF) 247 Page - Texas Instruments

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