AM5728 datasheet(246/415 Pages) TI1

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AM5729, AM5728, AM5726

SPRS953F – DECEMBER 2015 – REVISED MAY 2019

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Timing Requirements and Switching Characteristics

7.8

Display Subsystem – High-Definition Multimedia Interface (HDMI)

The High-Definition Multimedia Interface is provided for transmitting digital television audiovisual signals

from DVD players, set-top boxes and other audiovisual sources to television sets, projectors and other

video displays. The HDMI interface is aligned with the HDMI TMDS single stream standard v1.4a (720p

@60Hz to 1080p @24Hz) and the HDMI v1.3 (1080p @60Hz): 3 data channels, plus 1 clock channel is

supported (differential).

NOTE

For more information, see the High-Definition Multimedia Interface section of the device

TRM.

7.9

External Memory Interface (EMIF)

The device has a dedicated interface to DDR3 SDRAM. It supports JEDEC standard compliant DDR3

SDRAM devices with the following features:

•

16-bit or 32-bit data path to external SDRAM memory

•

Memory device capacity: 128Mb, 256Mb, 512Mb, 1Gb, 2Gb, 4Gb and 8Gb devices (Single die only)

•

One interface with associated DDR3 PHYs

NOTE

For more information, see the EMIF Controller section of the Device TRM.

7.10 General-Purpose Memory Controller (GPMC)

The GPMC is the unified memory controller that interfaces external memory devices such as:

•

Asynchronous SRAM-like memories and ASIC devices

•

Asynchronous page mode and synchronous burst NOR flash

•

NAND flash

NOTE

For more information, see the General-Purpose Memory Controller section of the Device

TRM.

7.10.1 GPMC/NOR Flash Interface Synchronous Timing

CAUTION

The IO Timings provided in this section are only valid for some GPMC usage

modes when the corresponding Virtual IO Timings or Manual IO Timings are

configured as described in the tables found in this section.

Table 7-25 and Table 7-26 assume testing over the recommended operating conditions and electrical

characteristic conditions below (see Figure 7-7, Figure 7-8, Figure 7-9, Figure 7-10, Figure 7-11, and

Figure 7-12).

Table 7-25. GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - Default

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

F12

tsu(dV-clkH)

Setup time, read gpmc_ad[15:0] valid before gpmc_clk high

2.69

F13

th(clkH-dV)

Hold time, read gpmc_ad[15:0] valid after gpmc_clk high

1.53

AM5728 Datasheet(PDF) 246 Page - Texas Instruments

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