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AM5728 Datasheet(PDF) 242 Page - Texas Instruments

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Part # AM5728
Description  Sitara Processors Silicon Revision 2.0
PDF  415 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

AM5728 Datasheet(HTML) 242 Page - Texas Instruments

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Copyright © 2015–2019, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics
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Product Folder Links: AM5729 AM5728 AM5726
242
AM5729, AM5728, AM5726
SPRS953F – DECEMBER 2015 – REVISED MAY 2019
www.ti.com
Table 7-22. Manual Functions Mapping for DSS VOUT2 IOSET1 (continued)
BAL
L
BALL NAME
VOUT2_IOSET1_MANUAL
1
VOUT2_IOSET1_MANUAL
2
VOUT2_IOSET1_MANUAL
3
VOUT2_IOSET1_MANUAL
4
CFG REGISTER
MUXMODE
A_DELAY
(ps)
G_DELAY
(ps)
A_DELAY
(ps)
G_DELAY
(ps)
A_DELAY
(ps)
G_DELAY
(ps)
A_DELAY
(ps)
G_DELAY
(ps)
4
G1
vin2a_hsync
0
2958
0
1059
0
4035
0
4905
0
CFG_VIN2A_HSYNC0_OUT
vout2_hsync
G6
vin2a_vsync
0
2752
0
853
0
3829
0
4699
0
CFG_VIN2A_VSYNC0_OUT
vout2_vsync
Manual IO Timings Modes must be used to ensure some IO timings for VOUT2. See Table 7-2 Modes Summary for a list of IO timings requiring
the use of Manual IO Timings Modes. See Table 7-23 Manual Functions Mapping for DSS VOUT2 IOSET2 for a definition of the Manual modes.
Table 7-23 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
Table 7-23. Manual Functions Mapping for DSS VOUT2 IOSET2
BALL
BALL NAME
VOUT2_IOSET2_MANUAL
1
VOUT2_IOSET2_MANUAL
2
VOUT2_IOSET2_MANUAL
3
VOUT2_IOSET2_MANUAL
4
CFG REGISTER
MUXMODE
A_DELAY
(ps)
G_DELAY
(ps)
A_DELAY
(ps)
G_DELAY
(ps)
A_DELAY
(ps)
G_DELAY
(ps)
A_DELAY
(ps)
G_DELAY
(ps)
6
E21
gpio6_14
1547
30
0
0
2298
0
3168
0
CFG_GPIO6_14_OUT
vout2_hsync
F20
gpio6_15
1773
31
209
0
2484
0
3354
0
CFG_GPIO6_15_OUT
vout2_vsync
F21
gpio6_16
1547
27
33
0
2345
0
3215
0
CFG_GPIO6_16_OUT
vout2_fld
B14
mcasp1_aclk
r
3738
2
2636
0
4925
0
5795
0
CFG_MCASP1_ACLKR_OUT
vout2_d0
G13
mcasp1_axr
2
2846
4
1730
0
4003
0
4873
0
CFG_MCASP1_AXR2_OUT
vout2_d2
J11
mcasp1_axr
3
2831
17
1498
0
3771
0
4541
0
CFG_MCASP1_AXR3_OUT
vout2_d3
E12
mcasp1_axr
4
3009
5
1879
0
4152
0
5022
0
CFG_MCASP1_AXR4_OUT
vout2_d4
F13
mcasp1_axr
5
3009
9
1802
0
4075
0
4945
0
CFG_MCASP1_AXR5_OUT
vout2_d5
C12
mcasp1_axr
6
2875
2
1792
0
4065
0
4935
0
CFG_MCASP1_AXR6_OUT
vout2_d6
D12
mcasp1_axr
7
2893
7
1717
0
3991
0
4861
0
CFG_MCASP1_AXR7_OUT
vout2_d7
J14
mcasp1_fsr
2729
13
1466
0
3739
0
4609
0
CFG_MCASP1_FSR_OUT
vout2_d1
E15
mcasp2_aclk
r
3753
13
2488
0
4761
0
5631
0
CFG_MCASP2_ACLKR_OUT
vout2_d8



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