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AM5728 Datasheet(PDF) 243 Page - Texas Instruments

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Part # AM5728
Description  Sitara Processors Silicon Revision 2.0
PDF  415 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

AM5728 Datasheet(HTML) 243 Page - Texas Instruments

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Copyright © 2015–2019, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics
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Product Folder Links: AM5729 AM5728 AM5726
243
AM5729, AM5728, AM5726
www.ti.com
SPRS953F – DECEMBER 2015 – REVISED MAY 2019
Table 7-23. Manual Functions Mapping for DSS VOUT2 IOSET2 (continued)
BALL
BALL NAME
VOUT2_IOSET2_MANUAL
1
VOUT2_IOSET2_MANUAL
2
VOUT2_IOSET2_MANUAL
3
VOUT2_IOSET2_MANUAL
4
CFG REGISTER
MUXMODE
A_DELAY
(ps)
G_DELAY
(ps)
A_DELAY
(ps)
G_DELAY
(ps)
A_DELAY
(ps)
G_DELAY
(ps)
A_DELAY
(ps)
G_DELAY
(ps)
6
B15
mcasp2_axr
0
2182
6
1022
0
3294
0
4164
0
CFG_MCASP2_AXR0_OUT
vout2_d10
A15
mcasp2_axr
1
2324
5
1179
0
3452
0
4322
0
CFG_MCASP2_AXR1_OUT
vout2_d11
D15
mcasp2_axr
4
2434
0
1374
0
3647
0
4517
0
CFG_MCASP2_AXR4_OUT
vout2_d12
B16
mcasp2_axr
5
2287
4
1164
0
3437
0
4307
0
CFG_MCASP2_AXR5_OUT
vout2_d13
B17
mcasp2_axr
6
3598
13
2339
0
4599
0
5469
0
CFG_MCASP2_AXR6_OUT
vout2_d14
A17
mcasp2_axr
7
2231
15
931
0
3204
0
4074
0
CFG_MCASP2_AXR7_OUT
vout2_d15
A20
mcasp2_fsr
1944
11
715
0
2988
0
3858
0
CFG_MCASP2_FSR_OUT
vout2_d9
C18
mcasp4_aclk
x
3241
8
2051
0
4324
0
5194
0
CFG_MCASP4_ACLKX_OUT
vout2_d16
G16
mcasp4_axr
0
2236
22
830
0
3090
0
3960
0
CFG_MCASP4_AXR0_OUT
vout2_d18
D17
mcasp4_axr
1
1803
16
505
0
2766
0
3636
0
CFG_MCASP4_AXR1_OUT
vout2_d19
A21
mcasp4_fsx
1901
19
541
0
2801
0
3671
0
CFG_MCASP4_FSX_OUT
vout2_d17
AA3
mcasp5_aclk
x
4582
2178
3499
1978
6020
1755
6890
1755
CFG_MCASP5_ACLKX_OUT
vout2_d20
AB3
mcasp5_axr
0
4628
1604
3505
1402
6025
1178
6895
1178
CFG_MCASP5_AXR0_OUT
vout2_d22
AA4
mcasp5_axr
1
4757
1237
3457
1063
5987
806
6857
806
CFG_MCASP5_AXR1_OUT
vout2_d23
AB9
mcasp5_fsx
4683
1485
3443
1280
5961
1059
6831
1059
CFG_MCASP5_FSX_OUT
vout2_d21
B26
xref_clk2
0
850
1900
1150
0
730
0
730
CFG_XREF_CLK2_OUT
vout2_clk
C23
xref_clk3
3075
19
1752
0
4012
0
4882
0
CFG_XREF_CLK3_OUT
vout2_de
Manual IO Timings Modes must be used to ensure some IO timings for VOUT3. See Table 7-2 Modes Summary for a list of IO timings requiring
the use of Manual IO Timings Modes. See Table 7-24 Manual Functions Mapping for DSS VOUT3 for a definition of the Manual modes.
Table 7-24 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.



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