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AM5728 Datasheet(PDF) 239 Page - Texas Instruments

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Part # AM5728
Description  Sitara Processors Silicon Revision 2.0
PDF  415 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

AM5728 Datasheet(HTML) 239 Page - Texas Instruments

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AM5729, AM5728, AM5726
www.ti.com
SPRS953F – DECEMBER 2015 – REVISED MAY 2019
Submit Documentation Feedback
Product Folder Links: AM5729 AM5728 AM5726
Timing Requirements and Switching Characteristics
Copyright © 2015–2019, Texas Instruments Incorporated
Table 7-20. VOUT3 IOSETs (continued)
SIGNALS
IOSET1
IOSET2 (1)
IOSET3 (1)
BALL
MUX
BALL
MUX
BALL
MUX
vout3_d3
M1
3
AE2
4
AH3
3
vout3_d2
L5
3
AE6
4
AH5
3
vout3_d1
M2
3
AD2
4
AG6
3
vout3_d0
M6
3
AD3
4
AH4
3
vout3_de
N9
3
AD9
4
vout3_vsync
R4
3
AF8
4
AF8
4
vout3_clk
P1
3
AF9
4
AF9
4
vout3_hsync
N7
3
AE9
4
AE9
4
vout3_fld
P9
3
AG8
4
(1) The VOUT3 interface when multiplexed onto balls mapped to the VDDSHV6 supply rail is restricted to operating in 1.8V mode only
(VDDSHV6 must be supplied with 1.8V). 3.3V mode is not supported. This must be considered in the pin mux programming and
VDDSHVx supply connections.
NOTE
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section Manual IO Timing Modes of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information see the Control Module chapter in the Device TRM.
Manual IO Timings Modes must be used to ensure some IO timings for VOUT1. See Table 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-21 Manual
Functions Mapping for DSS VOUT1 for a definition of the Manual modes.
Table 7-21 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.



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