AM5728 datasheet(236/415 Pages) TI1

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AM5729, AM5728, AM5726

SPRS953F – DECEMBER 2015 – REVISED MAY 2019

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Timing Requirements and Switching Characteristics

Table 7-17. DPI Video Output i (i = 1..3) MANUAL3 Switching Characteristics

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

tc(clk)

Cycle time, output pixel clock vouti_clk

6.06 (2)

tw(clkL)

Pulse duration, output pixel clock vouti_clk low

P*0.5-1

(1)

tw(clkH)

Pulse duration, output pixel clock vouti_clk high

P*0.5-1

(1)

td(clk-ctlV)

Delay time, output pixel clock vouti_clk transition to

output data vouti_d[23:0] valid

DPI1

2.85

5.56

DPI2, DPI3

2.78

5.91

td(clk-dV)

Delay time, output pixel clock vouti_clk transition to

output control signals vouti_vsync, vouti_hsync,

vouti_de, and vouti_fld valid

DPI1

2.85

5.56

DPI2, DPI3

2.78

5.91

(1) P = output vouti_clk period in ns.

(2) SERDES transceivers may be sensitive to the jitter profile of vouti_clk. A clock jitter cleaner such as the CDCE813 may be needed to

meet the required jitter masks of the SERDES transceiver. See Application Note SPRAC62 for general reference on a similar device

with the same interface.

Table 7-18. DPI Video Output i (i = 1..3) MANUAL4 Switching Characteristics

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

tc(clk)

Cycle time, output pixel clock vouti_clk

6.06 (2)

tw(clkL)

Pulse duration, output pixel clock vouti_clk low

P*0.5-1

(1)

tw(clkH)

Pulse duration, output pixel clock vouti_clk high

P*0.5-1

(1)

td(clk-ctlV)

Delay time, output pixel clock vouti_clk transition to output

data vouti_d[23:0] valid

DPI1,

DPI2,

DPI3

3.55

6.61

td(clk-dV)

Delay time, output pixel clock vouti_clk transition to output

control signals vouti_vsync, vouti_hsync, vouti_de, and

vouti_fld valid

DPI1,

DPI2,

DPI3

3.55

6.61

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