AM5728 datasheet(235/415 Pages) TI1

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AM5729, AM5728, AM5726

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SPRS953F – DECEMBER 2015 – REVISED MAY 2019

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Timing Requirements and Switching Characteristics

Table 7-15. DPI Video Output i (i = 1..3) Default Switching Characteristics

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

tc(clk)

Cycle time, output pixel clock vouti_clk

11.76

(2)

tw(clkL)

Pulse duration, output pixel clock vouti_clk low

DPI1, DPI2 (IOSET1),

DPI3

P*0.5-1

(1)

DPI2 (IOSET2)

P*0.5-

1.35 (1)

tw(clkH)

Pulse duration, output pixel clock vouti_clk high

DPI1, DPI2 (IOSET1),

DPI3

P*0.5-1

(1)

DPI2 (IOSET2)

P*0.5-

1.35 (1)

td(clk-dV)

Delay time, output pixel clock vouti_clk transition to

output data vouti_d[23:0] valid

DPI1

-2.5

2.5

DPI2 (IOSET1)

-2.5

2.5

DPI2 (IOSET2)

-2.5

2.5

DPI3 (IOSET1)

-2.5

2.5

DPI3 (IOSET2/3)

-2.5

2.5

td(clk-ctlV)

Delay time, output pixel clock vouti_clk transition to

output control signals vouti_vsync, vouti_hsync,

vouti_de, and vouti_fld valid

DPI1

-2.5

2.5

DPI2 (IOSET1)

-2.5

2.5

DPI2 (IOSET2)

-2.5

2.5

DPI3 (IOSET1)

-2.5

2.5

DPI3 (IOSET2/3)

-2.5

2.5

(1) P = output vouti_clk period in ns.

(2) All pads/balls configured as vouti_* signals are recommended to use slow slew rate by setting the corresponding

CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1). FAST slew setting is allowed, but results in faster edge rates on

the VOUTn bus, higher power/ground noise, and higher EMI emissions compared to SLOW slew rate.

(3) SERDES transceivers may be sensitive to the jitter profile of vouti_clk. A clock jitter cleaner such as the CDCE813 may be needed to

meet the required jitter masks of the SERDES transceiver. See Application Note SPRAC62 for general reference on a similar device

with the same interface.

Table 7-16. DPI Video Output i (i = 1..3) Alternate Switching Characteristics

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

tc(clk)

Cycle time, output pixel clock vouti_clk

6.06 (2)

tw(clkL)

Pulse duration, output pixel clock vouti_clk low

P*0.5-1

(1)

tw(clkH)

Pulse duration, output pixel clock vouti_clk high

P*0.5-1

(1)

td(clk-ctlV)

Delay time, output pixel clock vouti_clk transition to

output data vouti_d[23:0] valid

DPI1

1.51

4.55

DPI2 (IOSET1)

1.51

4.55

DPI2 (IOSET2)

1.51

4.55

DPI3

1.51

4.55

td(clk-dV)

Delay time, output pixel clock vouti_clk transition to

output control signals vouti_vsync, vouti_hsync,

vouti_de, and vouti_fld valid

DPI1

1.51

4.55

DPI2 (IOSET1)

1.51

4.55

DPI2 (IOSET2)

1.51

4.55

DPI3

1.51

4.55

(1) P = output vouti_clk period in ns.

(2) All pads/balls configured as vouti_* signals are recommended to use slow slew rate by setting the corresponding

CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1). FAST slew setting is allowed, but results in faster edge rates on

the VOUTn bus, higher power/ground noise, and higher EMI emissions compared to SLOW slew rate.

(3) SERDES transceivers may be sensitive to the jitter profile of vouti_clk. A clock jitter cleaner such as the CDCE813 may be needed to

meet the required jitter masks of the SERDES transceiver. See Application Note SPRAC62 for general reference on a similar device

with the same interface.

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