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AM5728 Datasheet(PDF) 231 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 231 Page - Texas Instruments |
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231 / 415 page  Copyright © 2015–2019, Texas Instruments Incorporated Timing Requirements and Switching Characteristics Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 231 AM5729, AM5728, AM5726 www.ti.com SPRS953F – DECEMBER 2015 – REVISED MAY 2019 Table 7-12. Manual Functions Mapping for VIP2 4B BALL BALL NAME VIP2_4B_MANUAL1 VIP2_4B_MANUAL2 CFG REGISTER MUXMODE A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 5 6 R6 gpmc_a0 1861 901 2102 660 CFG_GPMC_A0_IN - vin4b_d0 T9 gpmc_a1 1652 891 1955 583 CFG_GPMC_A1_IN - vin4b_d1 N9 gpmc_a10 0 0 0 0 CFG_GPMC_A10_IN - vin4b_clk1 P9 gpmc_a11 1783 1178 1975 1021 CFG_GPMC_A11_IN - vin4b_de1 P4 gpmc_a12 1903 853 2076 664 CFG_GPMC_A12_IN - vin4b_fld1 T6 gpmc_a2 1888 1212 2065 994 CFG_GPMC_A2_IN - vin4b_d2 T7 gpmc_a3 1839 1274 2025 1075 CFG_GPMC_A3_IN - vin4b_d3 P6 gpmc_a4 1868 1113 2058 869 CFG_GPMC_A4_IN - vin4b_d4 R9 gpmc_a5 1757 1079 2028 802 CFG_GPMC_A5_IN - vin4b_d5 R5 gpmc_a6 1800 670 2032 421 CFG_GPMC_A6_IN - vin4b_d6 P5 gpmc_a7 1967 898 2179 597 CFG_GPMC_A7_IN - vin4b_d7 N7 gpmc_a8 1731 959 1993 559 CFG_GPMC_A8_IN - vin4b_hsync1 R4 gpmc_a9 1766 1150 2022 834 CFG_GPMC_A9_IN - vin4b_vsync1 U4 mdio_d 1602 506 1931 283 CFG_MDIO_D_IN vin4b_d0 - V1 mdio_mclk 0 0 0 0 CFG_MDIO_MCLK_IN vin4b_clk1 - U5 rgmii0_rxc 1678 887 1987 663 CFG_RGMII0_RXC_IN vin4b_d5 - V5 rgmii0_rxctl 1595 932 1903 748 CFG_RGMII0_RXCTL_IN vin4b_d6 - W2 rgmii0_rxd0 1707 464 2010 160 CFG_RGMII0_RXD0_IN vin4b_fld1 - V4 rgmii0_rxd3 1662 1146 1943 996 CFG_RGMII0_RXD3_IN vin4b_d7 - W9 rgmii0_txc 1639 1195 1970 1006 CFG_RGMII0_TXC_IN vin4b_d3 - V9 rgmii0_txctl 1695 1226 1952 1113 CFG_RGMII0_TXCTL_IN vin4b_d4 - V6 rgmii0_txd1 1693 1118 1951 1003 CFG_RGMII0_TXD1_IN vin4b_vsync1 - U7 rgmii0_txd2 1522 1004 1895 685 CFG_RGMII0_TXD2_IN vin4b_hsync1 - V7 rgmii0_txd3 1777 957 2018 787 CFG_RGMII0_TXD3_IN vin4b_de1 - V2 uart3_rxd 1537 236 1762 0 CFG_UART3_RXD_IN vin4b_d1 - Y1 uart3_txd 1575 645 1933 276 CFG_UART3_TXD_IN vin4b_d2 - Manual IO Timings Modes must be used to ensure some IO timings for VIP2. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-13 Manual Functions Mapping for VIP2 3B IOSET2 for a definition of the Manual modes. Table 7-13 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers. |
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