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AM5728 Datasheet(PDF) 237 Page - Texas Instruments

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Part # AM5728
Description  Sitara Processors Silicon Revision 2.0
PDF  415 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

AM5728 Datasheet(HTML) 237 Page - Texas Instruments

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vouti_clk
vouti_vsync
vouti_hsync
vouti_d[23:0]
vouti_de
vouti_fld
data_1 data_2
data_n
odd
even
D1
D2
D3
D6
D6
D5
D6
D6
SWPS049-018
D4
vouti_clk
Falling-edge Clock Reference
Rising-edge Clock Reference
237
AM5729, AM5728, AM5726
www.ti.com
SPRS953F – DECEMBER 2015 – REVISED MAY 2019
Submit Documentation Feedback
Product Folder Links: AM5729 AM5728 AM5726
Timing Requirements and Switching Characteristics
Copyright © 2015–2019, Texas Instruments Incorporated
(1) P = output vouti_clk period in ns.
(2) SERDES transceivers may be sensitive to the jitter profile of vouti_clk. A clock jitter cleaner such as the CDCE813 may be needed to
meet the required jitter masks of the SERDES transceiver. See Application Note SPRAC62 for general reference on a similar device
with the same interface.
Figure 7-6. DPI Video Output(1)(2)(3)
(1) The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock.
(2) The polarity and the pulse width of vouti_hsync and vouti_vsync are programmable, refer to the DSS section of the device TRM.
(3) The vouti_clk frequency can be configured, refer to the DSS section of the device TRM.
NOTE
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in Table 4-3 and described in Control Module
chapter of the Device TRM.
In Table 7-19 are presented the specific groupings of signals (IOSET) for use with VOUT2.
Table 7-19. VOUT2 IOSETs
SIGNALS
IOSET1
IOSET2
BALL
MUX
BALL
MUX
vout2_d23
F2
4
AA4
6
vout2_d22
F3
4
AB3
6
vout2_d21
D1
4
AB9
6
vout2_d20
E2
4
AA3
6
vout2_d19
D2
4
D17
6
vout2_d18
F4
4
G16
6
vout2_d17
C1
4
A21
6
vout2_d16
E4
4
C18
6



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