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AM5728 Datasheet(PDF) 263 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 263 Page - Texas Instruments |
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263 / 415 page  gpmc_fclk gpmc_clk gpmc_csi gpmc_ben0 gpmc_ 1 ben gpmc_ _ale advn gpmc_wen gpmc_ad[15:0] gpmc_waitj DIR Address (MSB) Valid Address (LSB) Data OUT OUT FA0 FA1 FA9 FA10 FA3 FA25 FA29 FA12 FA27 FA28 FA0 FA10 GPMC_12 gpmc_a27 gpmc_a[10:1] 263 AM5729, AM5728, AM5726 www.ti.com SPRS953F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated Figure 7-18. GPMC / Multiplexed NOR Flash - Asynchronous Write - Single Word Timing(1) (1) In gpmc_csi, i = 0 to 7. In gpmc_waitj, j = 0 to 1. (2) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal direction on the GPMC data bus. 7.10.3 GPMC/NAND Flash Interface Asynchronous Timing CAUTION The IO Timings provided in this section are only valid for some GPMC usage modes when the corresponding Virtual IO Timings or Manual IO Timings are configured as described in the tables found in this section. Table 7-31 and Table 7-32 assume testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 7-19, Figure 7-20, Figure 7-21, and Figure 7-22). Table 7-31. GPMC/NAND Flash Interface Timing Requirements NO. PARAMETER DESCRIPTION MIN MAX UNIT GNF12 tacc(DAT) Data maximum access time (GPMC_FCLK Cycles) J (1) cycles - tsu(DV-OEH) Setup time, read gpmc_ad[15:0] valid before gpmc_oen_ren high 1.9 ns - th(OEH-DV) Hold time, read gpmc_ad[15:0] valid after gpmc_oen_ren high 1 ns |
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