XRT73L03IV datasheet(2/62 Pages) EXAR

2 / 62 page

XRT73L03

3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT

áç

PRELIMINARY

REV. P1.0.13

TRANSMIT INTERFACE CHARACTERISTICS

• Accepts either Single-Rail or Dual-Rail data from

Terminal Equipment and generates a bipolar signal

from the line

• Integrated Pulse Shaping Circuit.

• Built-in B3ZS/HDB3 Encoder (which can be dis-

abled)

• Contains Transmit Clock Duty Cycle Correction Cir-

cuit on-chip

• Generates pulses that comply with the ITU-T G.703

pulse template for E3 applications

• Generates pulses that comply with the DSX-3 pulse

template, as specified in Bellcore GR-499-CORE

and ANSI T1.102_1993

• Generates pulses that comply with the STSX-1

pulse template, as specified in Bellcore GR-253-

CORE

• Transmitter can be turned off in order to support

redundancy designs

RECEIVE INTERFACE CHARACTERISTICS

• Integrated Adaptive Receive Equalization (optional)

and Timing Recovery

• Declares and Clears the LOS defect per ITU-T

G.775 requirements for E3 and DS3 applications

• Meets Jitter Tolerance Requirements, as specified

in ITU-T G.823_1993 for E3 Applications

• Meets Jitter Tolerance Requirements, as specified

in Bellcore GR-499-CORE for DS3 Applications

• Declares Loss of Signal (LOS) and Loss of Lock

(LOL) Alarms

• Built-in B3ZS/HDB3 Decoder (which can be dis-

abled)

• Recovered Data can be muted while the LOS Con-

dition is declared

• Outputs either Single-Rail or Dual-Rail data to the

Terminal Equipment

• Receiver can be powered down in order to con-

serve power in redundancy designs

XRT73L03IV Datasheet(PDF) 2 Page - Exar Corporation

XRT73L03IV Datasheet(HTML) 2 Page - Exar Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

Datasheet Download

Link URL