AD9929BBCZ datasheet(26/64 Pages) AD

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AD9929

Rev. A | Page 26 of 64

P[0]

PIXEL

PERIOD

RGf[12]

P[48] = P[0]

Hf[24]

SHP[20]

CCD

SIGNAL

P[24]

P[12]

P[36]

Hr[0]

RGr[0]

SHD[40]

POSITION

NOTES

1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD.

2. DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN.

CDS

(INTERNAL)

tS1

Figure 17. High Speed Clock Default and Programmable Locations

FIXED CROSSOVER VOLTAGE

tPD

tRISE

tPD < tRISE

Figure 18. H-Clock Inverse Phase Relationship

NOTES

1. DCLK1 PHASE IS ADJUSTED BY SETTING THE DCLKPHASE REGISTER (ADDRESS 0x02)

2. DOUT PHASE CAN BE ADJUSTED BY SETTING THE DOUTPHASE REGISTER (ADDRESS 0x02)

P[0]

P[48] = P[0]

PIXEL

PERIOD

P[12]

P[24]

P[36]

DOUT

DCLK1

tOD

Figure 19. Digital Output Phase Adjustment

DIGITAL DATA OUTPUTS

The AD9929 DOUT[11:0] and DCLK phases are independently

programmable using the DOUTPHASE register (Address 0x02)

and DCLKPHASE register (Address 0x02). Refer to Figure 19.

AD9929BBCZ Datasheet(PDF) 26 Page - Analog Devices

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