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CY28441
Document #: 38-07679 Rev. **
Page 13 of 20
FS_A, FS_B,FS_C
VTT_PW RGD#
PW RGD_VRM
VDD Clock Gen
Clock State
Clock Outputs
Clock VCO
0.2-0.3mS
Delay
State 0
State 2
State 3
Wait for
VTT_PW RGD#
Sample Sels
Off
Off
On
On
State 1
Device is not affected,
VTT_PW RGD# is ignored
Figure 12. VTT_PWRGD# Timing Diagram
VTT_PWRGD# = Low
Delay
>0.25mS
S1
Power Off
S0
VDD_A = 2.0V
Sample
Inputs straps
S2
Normal
Operation
Wait for <1.8ms
Enable Outputs
S3
VTT_PWRGD# = toggle
VDD_A = off
Figure 13. Clock Generator Power-up/Run State Diagram
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