Data Sheet

ADF5902

Rev. 0 | Page 19 of 39

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2

DB1

DB0

0

00

0

0

0

01

1

0

0

01001M3

M2

M1

M0

IOL

RC5 RC4 RC3 RC2 RC1 RC0

C4(0) C3(0) C2(1) C1(1)

CONTROL

BITS

RESERVED

C5(0)

READBACK CONTROL

M3 M2 M1 M0

MUXOUT

0

0

0

0

TRISTATE OUTPUT

0

0

0

1

LOGIC HIGH

0

010

LOGIC LOW

0

0

1

1

R DIVIDER OUTPUT

0

1

0

0

N DIVIDER OUTPUT

0

101

RESERVED

0

110

RESERVED

0

111

CAL BUSY

1

000

RESERVED

1

001

RESERVED

1

010

RESERVED

1

0

1

1

R DIVIDER/2

1

1

0

0

N DIVIDER/2

1

101

RESERVED

1

110

RESERVED

1

1

1

1

RAMP STATUS TO MUXOIUT

IOL

0

1

IO LEVEL

3.3V LOGIC OUTPUTS

1.8V LOGIC OUTPUTS

1DBR = DOUBLE-BUFFERED REGISTER.

RC3 RC2 RC1 RC0

READBACK CONTROL

00

0

0

NONE

0

0

0

1

REGISTER 0

0

0

1

0

REGISTER 1

0

0

1

1

REGISTER 2

0

1

0

0

REGISTER 3

0

1

0

1

REGISTER 4

01

1

0

REGSITER 5

0

1

1

1

REGISTER 6

1

0

0

0

REGISTER 7

1

0

0

1

REGISTER 8

1

0

1

0

REGISTER 9

1

0

1

1

REGISTER 10

REGISTER 11

11

0

0

..

.

.

RESERVED

011

0

ADC READBACK

RC4

0

0

0

0

0

0

0

0

0

0

0

0

0

.

1

...

.

.

RC5

0

0

0

0

0

0

0

0

0

0

0

0

0

.

0

.

1

1

0

1

REGISTER 12

REGISTER 13 SEL = 0

11

1

0

0

0

0

0

111

1

000

0

0

1

0

0

00

0

1

REGISTER 17

0

010

1

1

0

0

REGISTER 13 SEL = 1

REGISTER 14 SEL = 0

REGISTER 15 SEL = 0

REGISTER 16 SEL = 0

REGISTER 14 SEL = 1

REGISTER 15 SEL = 1

REGISTER 16 SEL = 1

REGISTER 13 SEL = 2

REGISTER 14 SEL = 2

REGISTER 15 SEL = 2

REGISTER 16 SEL = 2

REGISTER 13 SEL = 3

REGISTER 14 SEL = 3

REGISTER 15 SEL = 3

REGISTER 16 SEL = 3

1

0

1

0

1

0

1

0

1

0

1

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

1

10

1

...

.

.

0

.

RESERVED

FREQ READBACK

RESERVED

RESERVED

Figure 27. Register 3 (R3)

REGISTER 3

Control Bits

With Bits[C5:C1] set to 00011, Register R3 is programmed.

Figure 27 shows the input data format for programming this

register.

Reserved

Bits[DB31:DB16] are reserved and must be set as shown in

Figure 27.

MUXOUT Control

Bits[DB15:DB12] control the on-chip multiplexer of the

ADF5902. See Figure 27 for the truth table.

Input/Output (I/O) Level

Bit DB11 controls the DOUT logic levels. Setting this bit to 0

sets the DOUT logic level to 1.8 V. Setting this bit to 1 sets the

DOUT logic level to 3.3 V.

Readback Control

Bits[DB10:DB5] control the readback data to DOUT on the

ADF5902. See Figure 27 for the truth table.