COPCH922C datasheet(21/26 Pages) NSC

21 / 26 page

Instruction Execution Time

Most instructions are single byte (with immediate addressing

mode instruction taking two bytes).

Most single instructions take one cycle time to execute.

Skipped instructions require x number of cycles to be

skipped, where x equals the number of bytes in the skipped

instruction opcode.

See the BYTES and CYCLES per INSTRUCTION table for

details.

Bytes and Cycles per

Instruction

The following table shows the number of bytes and cycles for

each instruction in the format of byte/cycle.

Arithmetic and Logic Instructions

[B]

Direct

Immed.

ADD

1/1

3/4

2/2

ADC

1/1

3/4

2/2

SUBC

1/1

3/4

2/2

AND

1/1

3/4

2/2

1/1

3/4

2/2

XOR

1/1

3/4

2/2

IFEQ

1/1

3/4

2/2

[B]

Direct

Immed.

IFGT

1/1

3/4

2/2

IFBNE

1/1

DRSZ

1/3

SBIT

1/1

3/4

RBIT

1/1

3/4

IFBIT

1/1

3/4

The following table shows the instructions assigned to un-

used opcodes. This table is for information only. The opera-

tions performed are subject to change without notice. Do not

use these opcodes.

Unused

Opcode

Instruction

Unused

Opcode

Instruction

NOP

LD A, [B]

NOP

C → HC

NOP

RET

X A, [X]

NOP

LD [B], #i

LDA,[X]

X A, [B]

NOP

Memory Transfer Instructions

Indirect

Direct

Immed.

Auto Incr & Decr

[B]

[X]

[B+, B−]

[X+, X−]

XA,*

1/1

1/3

2/3

1/2

1/3

LD A,*

1/1

1/3

2/3

2/2

1/2

1/3

LD B,Imm

1/1

(If B < 16)

LD B,Imm

2/3

(If B > 15)

LD Mem,Imm

2/2

3/3

2/2

LD Reg,Imm

2/3

Note 20: * = > Memory location addressed by B or X or directly.

Instructions Using A & C

CLRA

1/1

INCA

1/1

DECA

1/1

LAID

1/3

DCORA

1/1

RRCA

1/1

SWAPA

1/1

IFC

1/1

IFNC

1/1

Transfer of Control Instructions

JMPL

3/4

JMP

2/3

1/3

JSRL

3/5

JSR

2/5

JID

1/3

RET

1/5

RETSK

1/5

RETI

1/5

INTR

1/7

NOP

1/1

COPCH922C Datasheet(PDF) 21 Page - National Semiconductor (TI)

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