LPC2220 datasheet(28/49 Pages) PHILIPS

28 / 49 page

9397 750 14061

Product data sheet

Rev. 02— 30 May 2005

28 of 49

Philips Semiconductors

LPC2210/2220

16/32-bit ARM microcontrollers with external memory interface

6.20.3 Reset and wake-up timer

Reset has two sources on the LPC2210/2220: the RESET pin and watchdog reset. The

RESET pin is a Schmitt trigger input pin with an additional glitch ﬁlter. Assertion of chip

Reset by any source starts the wake-up timer (see wake-up timer description below),

causing the internal chip reset to remain asserted until the external Reset is de-asserted,

the oscillator is running, a ﬁxed number of clocks have passed, and the on-chip circuitry

has completed its initialization.

When the internal Reset is removed, the processor begins executing at address 0, which

is the Reset vector. At that point, all of the processor and peripheral registers have been

initialized to predetermined values.

The wake-up timer ensures that the oscillator and other analog functions required for chip

operation are fully functional before the processor is allowed to execute instructions. This

is important at power on, all types of Reset, and whenever any of the aforementioned

functions are turned off for any reason. Since the oscillator and other functions are turned

off during Power-down mode, any wake-up of the processor from Power-down mode

makes use of the wake-up timer.

The wake-up timer monitors the crystal oscillator as the means of checking whether it is

safe to begin code execution. When power is applied to the chip, or some event caused

the chip to exit Power-down mode, some time is required for the oscillator to produce a

signal of sufﬁcient amplitude to drive the clock logic. The amount of time depends on

many factors, including the rate of VDD ramp (in the case of power on), the type of crystal

and its electrical characteristics (if a quartz crystal is used), as well as any other external

circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing

ambient conditions.

6.20.4 External interrupt inputs

The LPC2210/2220 includes up to nine edge or level sensitive External Interrupt Inputs as

selectable pin functions. When the pins are combined, external events can be processed

as four independent interrupt signals. The External Interrupt Inputs can optionally be used

to wake up the processor from Power-down mode.

6.20.5 Memory mapping control

The Memory Mapping Control alters the mapping of the interrupt vectors that appear

beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the BANK0

external memory, or to the on-chip static RAM. This allows code running in different

memory spaces to have control of the interrupts.

6.20.6 Power control

The LPC2210/2220 supports two reduced power modes: Idle mode and Power-down

mode.

In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs.

Peripheral functions continue operation during Idle mode and may generate interrupts to

cause the processor to resume execution. Idle mode eliminates power used by the

processor itself, memory systems and related controllers, and internal buses.

LPC2220 Datasheet(PDF) 28 Page - NXP Semiconductors

LPC2220 Datasheet(HTML) 28 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

Datasheet Download

Link URL