© VITESSE SEMICONDUCTOR CORPORATION

Page 19

12/1/99

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC8151

2.488Gb/s SONET/SDH

STS-48/STM-16 Section Terminator

G52225-0, Rev. 2.9

Figure 16: Parallel Data Output Timing Diagram

Table 15: Parallel Data Output Timing

Note: Parallel output clock is synchronously generated 50/50 1/16th the frequency of the serial clock input (RXSCLKIN)

Parameter

Description

Min

Typ

Max

Units

Parallel output clock period

103.2

—6.45

ns

Propagation delay from falling edge of POUTCLK to

output edge of TXPOUT[15:0]

-500

—

500

ps

TXPOUT[15:0]

POUTCLK