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CONFIGURATION of DIGITAL FILTER

Mute Function (Pin MUTEB)

Oversampling Rate (Pin OSR2, OSR1)

Digital Filter Bypass (Pin BPB)

DAC8580

SLAS458B – JUNE 2005 – REVISED AUGUST 2005

The digital filter is configured through hardware as shown in Table 2.

Table 2. Configuration of Digital Filter

BPB

RSTB

OSR2

OSR1

MUTEB

DESCRIPTION

Don't

Don't

Don't

Don't

0

OUTPUT CLEAR. The output goes to mid-scale, 1.5 SCLK cycles after falling FSYNC

care

care

care

care

0

0

Don't

Don't

1

STANDARD DAC OPERATION (FILTER OFF)

care

care

DAC output updates with serial data, 1.5 SCLK after falling FSYNC

1

0

Don't

Don't

1

FILTER INITIALIZATION

care

care

Digital filter gets reset. DAC output goes to mid-scale after receiving SCLK rising edge.

0

1

Don't

Don't

1

STANDARD DAC OPERATION (FILTER COMPUTES IN THE BACKGROUND)

care

care

DAC output updates with serial data, 1.5 SCLK after falling FSYNC

1

1

0

0

1

2X oversampled OPERATION WITH FILTER ON

thereafter.

1

1

0

1

1

4X oversampled OPERATION WITH FILTER ON

thereafter.

1

1

1

0

1

8X oversampled OPERATION WITH FILTER ON

thereafter.

1

1

1

1

1

16X oversampled OPERATION WITH FILTER ON

DAC output updates with filter data, 1.5 SCLK after falling FSYNC and every SCLK thereafter.

Mute function is implemented by setting the DAC output voltage to mid-scale (~0 V). The MUTEB pin is active

low, and is synchronized with the frame. That is, the DAC latch and DAC output are immediately set to mid-scale

during the first update while the MUTEB pin is low. The MUTEB pin works independent of the serial data

transfer, or the digital filter. Neither the serial input, nor the digital filter data get interrupted or get lost while the

output is set at mid-scale with MUTEB. The first DAC update occurring after the MUTEB pin goes high sets the

DAC latch and DAC output to the next desired value. MUTEB pin must be kept at logic low level before power

up.

oversampling rate of the digital filter is set via pins OSR2 and OSR1.

OSR2 OSR1

OVERSAMPLING RATE

0

0

2

0

1

4

1

0

8

1

1

16

The DAC8580 can support these oversampling ratios as long as the oversampled update rate does not exceed

16 MSPS. The oversampling ratio should be set at power up. OSR1 and OSR2 pins must be kept at logic-low

level before power up.

The digital filter can be asynchronously bypassed via pin BPB. When pin BPB is active low, the digital filter is

bypassed. In this case, the DAC latch receives the data from the temporary register, not from the digital filter.

When the series input data is latched into the temporary register from the input shift register, the DAC latch and

DAC output are updated immediately with the new value of the temporary register. When pin BPB is high, digital

filter is not bypassed. The DAC latch is loaded with the output of the digital filter, not with the content of the

temporary register. The digital filter generates the data and transfers it to the DAC latch.

When the digital filter is bypassed, the filter keeps running. A bypass does not disrupt the internal computations

of the digital filter. When the BPB pin goes high, the oversampled operation resumes without any discontinuity of

16