HD64F2145 datasheet(382/829 Pages) RENESAS

382 / 829 page

Rev. 2.0, 08/02, page 342 of 788

15.3.1

Receive Shift Register (RSR)

RSR is a shift register used to receive serial data that converts it into parallel data. When one

frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly

accessed by the CPU.

15.3.2

Receive Data Register (RDR)

RDR is an 8-bit register that stores receive data. When the SCI has received one frame of serial

data, it transfers the received serial data from RSR to RDR where it is stored. After this, RSR can

receive the next data. Since RSR and RDR function as a double buffer in this way, continuous

receive operations can be performed. After confirming that the RDRF bit in SSR is set to 1, read

RDR for only once. RDR cannot be written to by the CPU. RDR is initialized to H’00.

15.3.3

Transmit Data Register (TDR)

TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it

transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered

structures of TDR and TSR enables continuous serial transmission. If the next transmit data has

already been written to TDR when one frame of data is transmitted, the SCI transfers the written

data to TSR to continue transmission. Although TDR can be read from or written to by the CPU at

all times, to achieve reliable serial transmission, write transmit data to TDR for only once after

confirming that the TDRE bit in SSR is set to 1. TDR is initialized to H’FF.

15.3.4

Transmit Shift Register (TSR)

TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first

transfers transmit data from TDR to TSR, then sends the data to the TxD pin. TSR cannot be

directly accessed by the CPU.

HD64F2145 Datasheet(PDF) 382 Page - Renesas Technology Corp