HD64F2145 datasheet(385/829 Pages) RENESAS

385 / 829 page

Rev. 2.0, 08/02, page 345 of 788

15.3.6

Serial Control Register (SCR)

SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt

requests, and selection of the transfer clock source. For details on interrupt requests, refer to

section 15.8, Interrupt Sources.

Bit

Bit Name

Initial Value

R/W

Description

TIE

R/W

Transmit Interrupt Enable

When this bit is set to 1, a TXI interrupt request is

enabled.

RIE

R/W

Receive Interrupt Enable

When this bit is set to 1, RXI and ERI interrupt

requests are enabled.

R/W

Transmit Enable

When this bit is set to 1, transmission is enabled.

R/W

Receive Enable

When this bit is set to 1, reception is enabled.

MPIE

R/W

Multiprocessor Interrupt Enable (enabled only when

the MP bit in SMR is 1 in asynchronous mode)

When this bit is set to 1, receive data in which the

multiprocessor bit is 0 is skipped, and setting of the

RDRF, FER, and ORER status flags in SSR is

disabled. On receiving data in which the

multiprocessor bit is 1, this bit is automatically

cleared and normal reception is resumed. For

details, refer to section 15.5, Multiprocessor

Communication Function.

TEIE

R/W

Transmit End Interrupt Enable

When this bit is set to 1, a TEI interrupt request is

enabled.

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