HD64F2145 datasheet(388/829 Pages) RENESAS

388 / 829 page

Rev. 2.0, 08/02, page 348 of 788

Bit

Bit Name

Initial Value

R/W

Description

4FER

R/(W)*

Framing Error

[Setting condition]

• When the stop bit is 0

[Clearing condition]

• When 0 is written to FER after reading FER =

In 2-stop-bit mode, only the first stop bit is

checked.

PER

R/(W)*

Parity Error

[Setting condition]

• When a parity error is detected during

reception

[Clearing condition]

• When 0 is written to PER after reading PER =

TEND

Transmit End

[Setting conditions]

• When the TE bit in SCR is 0

• When TDRE = 1 at transmission of the last bit

of a 1-byte serial transmit character

[Clearing conditions]

• When 0 is written to TDRE after reading TDRE

= 1

• When a TXI interrupt request is issued

allowing the DTC to write data to TDR

MPB

Multiprocessor Bit

MPB stores the multiprocessor bit in the receive

frame. When the RE bit in SCR is cleared to 0 its

previous state is retained.

MPBT

R/W

Multiprocessor Bit Transfer

MPBT stores the multiprocessor bit to be added to

the transmit frame.

Note:* Only 0 can be written, to clear the flag.

HD64F2145 Datasheet(PDF) 388 Page - Renesas Technology Corp

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