DP83821 datasheet(26/86 Pages) NSC

26 / 86 page

3.0 Functional Description (Continued)

www.national.com

3.13.3.1 Transmit State Machine

The transmit state machine has the following states:

The transmit state machine manipulates the following internal data spaces:

Inputs to the transmit state machine include the following events:

Table 3-8 Transmit State Tables

txIdle

The transmit state machine is idle.

txDescRefr

Waiting for the "refresh" transfer of the link field of a completed descriptor from the PCI bus.

txDescRead

Waiting for the transfer of a complete descriptor from the PCI bus into the

TxDescriptorCache.

txFifoBlock

Waiting for free space in the TxDataFIFO to reach TxFillThreshold.

txFragRead

Waiting for the transfer of a fragment (or portion of a fragment) from the PCI bus to the

TxDataFIFO.

txDescWrite

Waiting for the completion of the write of the cmdsts field of an intermediate transmit

descriptor (cmdsts.MORE == 1) to host memory.

txAdvance

(transitory state) Examine the link field of the current descriptor and advance to the next

descriptor if link is not NULL.

TXDP

A 32-bit register that points to the current transmit descriptor. If priority queueing is enabled,

this points to the available transmit descriptor with the highest priority.

CTDD

Current Transmit Descriptor Done. An internal bit flag that is set when the current transmit

descriptor has been completed, and ownership has been returned to the driver. It is cleared

whenever TXDP is loaded with a new value (either by the state machine, or the driver).

TxDescCache

An internal data space equal to the size of the maximum transmit descriptor supported.

descCnt

Count of bytes remaining in the current descriptor.

fragPtr

Pointer to the next unread byte in the current fragment.

txFifoCnt

Current amount of data in the txDataFifo in bytes.

txFifoAvail

Current amount of free space in the txDataFifo in bytes (size of the txDataFifo - txFifoCnt).

CR:TXEN

Driver asserts the TXEN bit in the command register. If priority queueing is enabled, this

corresponds to a specific priority queue.

XferDone

Completion of a PCI bus transfer request.

FifoAvail

TxFifoAvail is greater than TxFillThreshold.

state

event

next state

actions

txIdle

CR:TXEN && !CTDD

txDescRead

start a burst transfer at address TXDP and a

length derived from TXCFG.

CR:TXEN && CTDD

txDescRefr

start a burst transfer to refresh the link field of the

current descriptor.

txDescRefr

XferDone

txAdvance

txDescRead

XferDone && OWN

txFIFOblock

XferDone && !OWN

txIdle

set ISR:TXIDLE.

txFIFOblock

FifoAvail

txFragRead

start a burst transfer into the TxDataFIFO from

fragPtr. The length will be the minimum of

txFifoAvail and descCnt.

Decrement descCnt accordingly.

(descCnt == 0) && MORE

txDescWrite

start a burst transfer to write the status back to the

descriptor, clearing the OWN bit.

(descCnt == 0) && !MORE

txAdvance

write the value of TXDP to the txDataFIFO as a

handle.

txFragRead

XferDone

txFIFOblock

txDescWrite

XferDone

txAdvance

DP83821 Datasheet(PDF) 26 Page - National Semiconductor (TI)

DP83821 Datasheet(HTML) 26 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86

Datasheet Download

Link URL