DP83821 datasheet(64/86 Pages) NSC

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4.0 Register Set (Continued)

4.2.26 Management Information Base Control Register

The MIBC register is used to control access to the statistics block and the warning bits and to control the collection of

management information statistics.

Tag: MIBC

Size: 32 bits

Hard Reset: 00000002h

Offset: 005ch

Access: Read Write

Soft Reset: 00000002h

bit

tag

description

usage

31-4

unused

MIBS

MIB Counter Strobe

Writing a 1 to this bit location causes the counters in all enabled blocks to

increment by 1, providing a single-step test function. The MIBS bit is

always read back as 0. This bit is used for test purposes only and

should be set to 0 for normal counter operation.

ACLR

Clear all counters

When set to a 1, this bit forces all counters to be reset to 0. This bit is

always read back as 0.

FRZ

Freeze all counters

When set to a 1, this bit forces count values to be frozen such that a read of

the statistic block will represent management statistics at a given instant in

time. When set to 0, the counters will increment normally and may be read

individually while counting.

WRN

Warning Test Indicator

This field is read only. This bit is set to 1 when all statistic counters have

reached their respective overflow warning condition. WRN will be cleared

after one or more of the statistic counters have been cleared.

DP83821 Datasheet(PDF) 64 Page - National Semiconductor (TI)