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MBF110PFWLPES Datasheet(PDF) 6 Page - fujitsu semiconductor

Part # MBF110PFWLPES
Description  Solid-State Fingerprint Sensor
PDF  24 Pages
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Manufacturer  FUJITSU [fujitsu semiconductor]
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MBF110PFWLPES Datasheet(HTML) 6 Page - fujitsu semiconductor

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Pr
eliminar
y
Solid-State Fingerprint Sensor
2
Fujitsu Microelectronics, Inc.
After the row capture is completed, the High-Order ColumnAddress
Register (CAH) and Low-Order ColumnAddress Register (CAL)
must be programmed to select an element within the captured row to
be digitized. Writing to CAL causes the analog-to-digital (A/D)
converter to digitize the difference between the outputs of the two
sample-and-holds of the selected column cell.The output of theA/D
converter is accessed by reading the CAL register.
Rows can be accessed in any order; however, the selected row must be
captured before the column cells are read.The column cells within a
row can be accessed in any order.
Special Features
There are two programmable open-drain outputs that can be used
for driving LEDs.
The CLKOUT pin can be enabled to output a square-wave clock of
the same frequency as the oscillator clock. CLKOUT can be used to
drive external circuitry. When ENCLK is high, the clock signal is
present at the CLKOUT pin. When ENCLK is low or unconnected,
the CLKOUT output is held low.
MBF110 Pin Information for SOP (VSPA) 80/1
Pin
Number
Pin
Name
Type
Description
Notes
34
A3
Input
Address Inputs
Address signals connected to these pins select a register to read from or write to dur-
ing data transfer.
35
A2
36
A1
37
A0
38
CE1
Chip Enable, Active Low
When CE1 is low and CE2 is high, the chip is selected.
39
CE2
Chip Enable, Active High
When CE1 is low and CE2 is high, the chip is selected.
40
RD
Read Enable, Active Low
This pin must be low while WR is high and the chip selected in order to read a register
on the chip.
17
WR
Write Enable, Active Low
This pin must be low while the chip is selected to write to a register on the chip.
18
D7
Bi-directional
Data Bus
Inputs when WR is low and chip is selected. Outputs when RD is low, WR is high, and
chip is selected.
19
D6
21
D5
22
D4
24
D3
25
D2
26
D1
27
D0
32
CLKOUT
Output
Clock Output
This pin outputs the oscillator clock frequency when ENCLK is high.
31
ENCLK
Input
Enable Clock Output
A high on this pin enables the CLKOUT pin. A low on this pin holds CLKOUT low.
ENCLK has an internal pull-down resistor.
15
LED1
Open-drain
Output
LED driver
This pin can be used to drive an LED.
14
LED2
Open-drain
Output
3
SETCUR
Input
Set Discharge Current
Place an external resistor R1 (200K – 680K ohms) between this pin and ground.
Typical: FPS110, R1 = 680K; FPS110B, R1 = 200K; FPS110E, R1 = 200K
2
N/A
Reserved pin
Must be left disconnected.
13
TEST
20, 33
VDD
Power
Digital Power Supply
1VDDA
Analog Power Supply



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