STA450A datasheet(10/66 Pages) STMICROELECTRONICS

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STA450A

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According to the chosen oversampling factor, the following table permits to configure the dividers of the Audio PLL:

See also the register description.

1.3 PCM Output Interface

The decoded audio data can be output in serial PCM format.

The interface consists of the following signals:

SDO PCM Serial data output

SCKT PCM serial Clock Output

LRCKT Left/Right Channel Selection Clock

The output samples precision is selectable from 16 to 24 bits/word by setting the output precision (16, 18, 20

and 24bits) with the HOST_PCMCNF register; the same register is used to output data either with the most sig-

nificant bit first (MS) or least significant bit first (LS).

Figure 6 gives a description of the STA450A PCM Output Formats.

The SCKT signal is the bit clock for the serial output and is derived from the PCMCLK (OCLK) as in the following

formula:

SCKT = OCLK / 2*(HOST_PCMDIV + 1)

The number of bits to be transmitted to the DAC during one LRCKT clock period depends on the DAC precision

(16, 18, 20 or 24bits) and on the mode used to transmit the data (LRCKT_period equal to 16x2 or 32x2

SCKT_period - refer to figure 6).

The value of the HOST_PCMDIV register must be set accordingly to the previous consideration and to the DAC

Oversampling Factor (O_FAC).

– LRCKT_period = 16x2 SCKT_period

HOST_PCMDIV = (O_FAC/64) - 1

– LRCKT_period = 32x2 SCKT_period

HOST_PCMDIV = (O_FAC/128) - 1

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