STA450A datasheet(3/66 Pages) STMICROELECTRONICS

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STA450A

PIN FUNCTION

N°

Type

Function

Pad Description

1,6,53

NU(IT_1),

NU(IT_2),

NU(IT_0)

Not Used (must be connected to

ground in functional mode)

Schmitt Trigger Buffer

2,9,15,23,

30,37,44,5

0,57,62,69

,76

GND1…,GND12

Ground

3,10,16,

24,31,38,4

5,51,58,63

,70,77

VDD1…,VDD12

1.8V Core Supply Voltage

TEST0

Test Pin (must be connected to

ground in functional mode)

Analog Pad

CLK_IN

Clock Input

Schmitt Trigger Buffer

TESTB

Test Pin

Input Pad Buffer with Active Pull-Up

CAP_RST (GPIO_4)

I/O

CAP Reset

Bi Dir Pad, 4mA Output Buffer with

Slew Rate Control

11,32,52,7

VDD_IO1,…

VDD_IO4

3.3V I/O Supply Voltage

CLK_OUT

Clock Out

4mA Output Buffer with Slew Rate

Control

SCL_M

I2C Master Serial Clock

4mA Output Buffer with Slew Rate

Control

SDA_M

I/O

I2C Master Serial Data

Bi Dir Pad, 4mA Output Buffer with

Slew Rate Control

17,27,28,4

NU(FIT_0),

NU(FIT_3),

NU(FIT_4), NU(FIT_1)

Not Used (must be connected to

ground in functional mode)

Schmitt Trigger Buffer

SCAN_MODE

Scan Mode (must be connected to

ground in functional mode)

Input Pad Buffer

APLL_GND

Analog Ground for Audio PLL

APLL_VDD

1.8V Analog Supply for Audio PLL

FILT_0

PLL Filter

Analog Pad

Not Used

25,26

CLK_M1, CLK_M0

Selection of Input Clock for the DSP

core and peripherals

Input Pad Buffer

PLL_SYNC (FIT_5)

Fractional Audio PLL Sync.

Schmitt Trigger Buffer

PCDC

I/O

PC Bitstream Data Clock

Schmitt Trigger Bi Dir Pad, 4mA

Output Buffer with Slew Rate Control

PCSD

I/O

PC Bitstream Serial Data

Schmitt Trigger Bi Dir Pad, 4mA

Output Buffer with Slew Rate Control

35,41,46

NU(USSIO0_LRCLK)

NU(USSIO1_LRCLK)

NU(USSIO2_LRCLK)

I/O

Not Used (must be connected to

ground in functional mode)

Schmitt Trigger Bi Dir Pad, 4mA

Output Buffer with Slew Rate Control

NU(REQ)

Not used

4mA Output Buffer with Slew Rate

Control

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